Pointer for defining the data by controlling merge switches

ABSTRACT

In a microprogrammed data processing system the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which strips zone bits, sign, exponent and non-operand characters from the operand when the operand is received from memory and appends the zone bits, sign, exponent and non-operand characters to the resultant operand when stored into memory. The control signals for stripping and appending information is enabled by shifter logical elements.

RELATED APPLICATIONS

The following U.S. patent applications filed on an even date with theinstant application and assigned to the same assignee as the instantapplication are related to the instant application.

1. "Prediction of Number of Data Words Transferred and Cycle at WhichData is Available" by Richard T. Flynn and Jerry L. Kindell, and havingU.S. Ser. No. 000,223 filed on Jan. 2, 1979, and assigned to the sameassignee as named herein.

2. "Short Operand Alignment and Merge Operation" by Richard T. Flynn andJerry L. Kindell, and having U.S. Ser. No. 000,401, filed on Jan. 2,1979, and assigned to the same assignee as named herein.

3. "Long Operand Alignment and Merge Operation" by Jerry L. Kindell andRichard T. Flynn, and having U.S. Ser. No. 000,399, filed on Jan. 2,1979, and assigned to the same assignee as named herein.

4. "Improved Apparatus and Method for Rewrite Data and Insertion in aTwo Descriptor Instruction" by Jerry L. Kindell and Richard T. Flynn,and having U.S. Ser. No. 000,393 filed on Jan. 2, 1979 and assigned tothe same assignee as named herein.

5. "Improved Apparatus and Method for Rewrite Data Insertion in a ThreeDescriptor Instruction" by Jerry L. Kindell and Richard T. Flynn, andhaving U.S. Ser. No. 000,221, filed on Jan. 2, 1979 and assigned to thesame assignee as named herein.

6. "Leading Zero Count Formation" by Richard T. Flynn and Jerry L.Kindell, and having U.S. Ser. No. 000,232, filed on Jan. 2, 1979, andassigned to the same assignee as named herein.

7. "Effective Digit Count on A Resultant Operand" by Jerry L. Kindelland Richard T. Flynn, and having U.S. Ser. No. 000,222, filed on Jan. 2,1979, and assigned to the same assignee as named herein.

8. "Numeric Data Fetch--Alignment of Data Including Scale FactorDifference" by Jerry L. Kindell and Richard T. Flynn, and having U.S.Ser. No. 000,220, filed on Jan. 2, 1979, and assigned to the sameassignee as named herein.

9. "Apparatus for Insertion of Corrected Overpunched Digit Into IncomingOperand Stream" by Jerry L. Kindell and Richard T. Flynn, and havingU.S. Ser. No. 000,392 filed on Jan. 2, 1979 and assigned to the sameassignee as named herein.

10. "Apparatus for Merge Control of an Exponent Split Across a WordBoundary" by Jerry L. Kindell and Richard T. Flynn, and having U.S. Ser.No. 000,397, filed on Jan. 2, 1979 and assigned to the same assignee asnamed herein.

11. "Apparatus and Method for Insertion of a Character Data Group in aWord Character Group" by Richard T. Flynn and Jerry L. Kindell, andhaving U.S. Ser. No. 000,396, filed on Jan. 2, 1979 and assigned to thesame assignee as named herein.

12. "Apparatus for Improved Rounding Operation For Short Operand" byRichard T. Flynn and Jerry L. Kindell, and having U.S. Ser. No. 000,398,filed on Jan. 2, 1979 and assigned to the same assignee as named herein.

13. "Apparatus for Improved Rounding Operation For Long Operand" byRichard T. Flynn and Jerry L. Kindell and having U.S. Ser. No. 000,400,filed on Jan. 2, 1979, and assigned to the same assignee as namedherein.

14. "Vector Branch Indicators to Control Firmware" by Richard T. Flynnand Jerry L. Kindell, having U.S. Ser. No. 000,224, filed on Jan. 2,1979, and assigned to the same assignee as named herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the processing of decimal numericinstructions by a microprogrammed data processing system and moreparticularly to the stripping and appending of non-decimal digitcharacters to the operand.

2. Description of the Prior Art

Digital computer systems execute instructions calling for the processingof decimal operands. The decimal operands are made up of a plurality ofwords with each word containing a plurality of decimal characters. Aword may also contain information that is not included in the operand.The decimal characters includes decimal digits being in the form of4-bit decimal digits packed up to eight decimal digits per word, or9-bit ASCII or EBCDIC decimal digits packed up to four decimal digitsper word. The decimal characters also include sign characters and, forfloating point instructions, exponent characters.

The operands are stored in memory and, in the prior art, are transferredto an arithmetic unit where the words are stripped of sign characters,exponent characters and non-operand characters. In addition, the 9 bitdecimal digits are stripped of the zone bits and packed into words of upto eight decimal digits per word. This readily permits decimalarithmetic wherein operands containing 9-bit decimal digits areprocessed with 4-bit decimal digits in response to the instructioncalling for a decimal arithmetic operation of the two operands.

Before the resulting operand is stored back in memory, however, thenecessary sign, exponent and non-operand characters must be added, aswell as the zone bits if the resulting operand is made up of 9-bitcharacters.

The Honeywell 6000 computing system performed the merging of sign, zonebits, exponent and non-operand characters along with the decimal digitsinto the words of the resulting operand using considerable combinationallogic.

Microprogrammed computers perform this merging operation bymicroprogrammed subroutines shifting the decimal digits of thearithmetic result into the proper position within the word for andadding the sign, exponent, zone bits and non-operand information. Sincethe microprogrammed subroutines performed in a serial fashion, thesystem throughput was degraded.

OBJECTS OF THE INVENTION

Accordingly, it is an object of this invention to increase the systemthroughput during the processing of decimal arithmetic instructions.

It is another object of this invention to increase the system throughputduring the merging of sign, exponents, zone bits and non-operandcharacters with the decimal digits of the resultant operand during theprocessing of decimal arithmetic instructions.

SUMMARY OF THE INVENTION

The above objects and advantages of the present invention areaccomplished in a preferred embodiment of the present invention whichincludes a data processing system including a cache memory which storesinstructions including descriptors, a control unit which receives theinstructions and descriptors from cache, an execution control unit whichreceives the instructions from the control unit to generate a series ofmicrowords which enables the data processing system to execute theinstructions.

The system also includes a decimal unit which is operative during theprocessing of decimal arithmetic instructions, and under microprogramcontrol receives the descriptors from the control unit and receives theoperands from cache. In the decimal unit the operand characters arestripped of zone bits, and also if applicable, sign, exponent andnon-operand characters and assembled into words of up to eight decimaldigits per word for transfer to an execution unit. The operand word isstripped of non 4-bit decimal digit information on the cycle the operandword is processed through the decimal unit.

The execution unit performs the decimal arithmetic specified by theinstruction on the two operands and transfers the resulting thirdoperand to the decimal unit in the form of words made up of 4-bitdecimal digits.

The decimal unit processes the third operand as specified by adescriptor describing the third operand. The descriptor enables thelogic in the decimal unit during a store operation to merge the sign,exponents, zone bits and non-operand characters with the decimal digitsand transfer the merged words to cache at an address specified by thedescriptor under microprogram control. The information is merged intothe operand word on the cycle the word is processed through the decimalunit.

The invention comprises a plurality of switches and means forcontrolling the switches. A four level ZSMR switch 730-180 adds thesign, exponent and non-operand characters (rewrite) to the operand asthe decimal digits of the third operand are received from the executionunit, processed in the decimal unit and transferred to cache.

Level 0 of the ZSMR switch expands the 4-bit decimal digit from a 32-bitword to a 36-bit word. Leading or trailing sign characters are added tothe operand through level 1 of the ZSMR switch. One position of level 1of the ZSMR switch is selected if the descriptor specifies 4-bitcharacters and two adjacent positions of level 1 of the ZSMR swtich areselected if the descriptor specifies 9-bit characters. The selection ismade by the SIGNM output signals of the shifter 730-118.

The exponent is added to the third operand, specified by the descriptoras being floating point operands, through level 2 of the ZSMR switch730-180. Two adjacent signals at logical ZERO input the EXPM shifter730-122 to select two of the EXPM 0-7 output signals of the shifter toactivate the two selected exponent positions of the trailing word of thefloating point third operand.

The rewrite information is added to the leading word and trailing word,if applicable, through level 3 of the ZSMR switch 730-180. The REWUMshifter 730-149 selects the non-operand positions of the leading operandword and the REWLM shifter 730-114 selects the non-operand positions ofthe trailing word for transferring the rewrite information through theZEWR switch 730-178 and through the selected positions of the ZSMRswitch 730-180.

During the load operation, that is, the decimal unit receiving theoperand from cache for alignment, the sign and exponent characters arestripped from the operands in the ZID switch 730-150 under ciontrol ofthe ZIDML shifter 730-128 and the ZIDMU shifter 730-130 which mask outinformation to the right of the least significant decimal digit in theword of the operand containing the least significant decimal digit; andmasks out information to the left of the most significant digit.

Also during the load operation the ZCRDGM shifter 730-145 selects thelevel 2 position of the ZID switch 730-150 for replacement of theoverpunched sign character with the specified decimal digit in an ASCIIor EBCDIC operand. The overpunched sign decimal character is a single9-bit character which is coded to indicate a sign and a decimal digit.

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further objects and advantages will be better understood from thefollowing description when considered in connection with theaccompanying drawings. It is to be expressly understood, however, thateach of the drawings is given for the purpose of illustration anddescription only and are not intended as a definition of the limits ofthe present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overall block diagram of the host processor. The cache unitand system integration unit are shown connected to the host processor.

FIG. 2 is a block diagram of the execution unit and a portion of thecharacter unit of the host processor.

FIG. 3 is a detailed block diagram of the decimal unit.

FIG. 4 is an overall block diagram of the decimal unit.

FIG. 5 shows the instruction and descriptor formats for two decimalnumeric instructions.

FIG. 6 is a logic diagram of the leading zero count circuits.

FIG. 7 is a logic diagram of the effective digit circuits.

FIG. 8 is a diagram of the vector branch logic.

General Description of Processor 700--FIG. 1

Referring to FIG. 1, it is seen that a host processor 700 includes anexecution control unit 701, a control unit 704, an execution unit 714, acharacter unit 720, an auxiliary arithmetic and control unit (AACU) 722,a multiply-divide unit 728, and a decimal unit 730 which areinterconnected as shown. Additionally, the control unit 704 has a numberof interconnections to the cache 750 as shown.

The execution control unit 701 includes an execution control storeaddress preparation and branch unit 701-1, and an execution controlstore 701-2. The store 701-2 and unit 710-1 are interconnected via buses701-3 and 701-6 as shown.

The control unit 704 includes a control logic unit 704-1, a controlstore 704-2, an address preparation unit 704-3, data and address outputcircuit 704-4, an XAQ register section 704-5 which interconnect asshown.

The control unit 704 provides the necessary control for performingaddress preparation operations, instruction fetching/executionoperations and the sequential control for various cycles of operationand/or machine states. The control is generated by logic circuits ofblock 704-1 and by the execution control unit 701 for the variousportions of the control unit 704.

The XAQ register section 704-5 includes a number of program visibleregisters such as index registers, an accumulator register, and quotientregister. Other program fisible registers such as the instructioncounter and address registers are included within the addresspreparation unit 704-3.

As seen from FIG. 1, the section 704-5 receives signals from unit 704-3representative of the contents of the instruction counter via lines RIC00-17. Also, lines ZRESA 00-35 apply output signals from the executionunit 714 corresponding to the results of operations performed uponvarious operands. The section 704-5 also receives an output signal fromthe auxiliary arithmetic and control unit via lines RAAUO-8.

The section 704-5 provides signals representative of the contents of oneof the registers included within the section as an input to the addresspreparation unit 704-3 via the lines ZXO-20 and ZXA 24-35. The addresspreparation unit 704-3 forwards the information through a switch to theexecution unit 714 via the lines ZDO 0-35. Similarly, the contents ofcertain ones of the registers contained within section 704-5 can betransferred to the execution unit 714 via the lines ZEB 00-35. Lastly,the contents of selected ones of these registers can be transferred fromsection 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contentsof various registers contained therein and applies the resultantlogical, effective and/or absolute addresses for distribution to otherunits along the lines ASFA 00-35. The address preparation unit 704-3receives the results of operations performed on a pair of operands bythe execution unit 714 via the lines ZRESB 00-35. The unit 704-4receives signals representative of the contents of a pair of basepointer registers from the control logic unit 701 via the lines RBASAand RBASAO-1. Outputs from the multiply/divide unit 728 are applied tothe address preparation unit 704-3. Lastly, the contents of a secondaryinstruction register (RSIR) are applied as input to the unit 704-3 viathe lines RSIR 00-35.

The data and address output circuits 704-4 generate the cache memoryaddress signals which it applies to the cache unit 750 via the linesRADO/ZADO 00-35. These address signals correspond to the signals appliedto one of the sets of input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35selected by switches included within the circuits of block 704-4. Also,word address signals are applied via the lines ASFA 32-33.

The control logic unit 704-1 provides data paths which have an interfacewith various units included within the cache unit 750. The lines ZIB00-35 provide an interface cache unit 750. The lines ZIB 00-35 providean interface with an instruction buffer included within he cache 750.The lines ZDI 00-35 are used to transfer data signals from the cache 750to the control logic unit 704-1.

As seen from FIG. 1, the control logic unit 704-1 provides a number ofgroups of output signals. These output signals include the contents ofcertain registers, as for example, a basic instruction register (RBIR)whose contents are applied as an input to control store 704-2 via thelines RBIR 18-27. The control logic unit 704-1 receives certain controlsignals read out from control store 704-2 via the lines CDSD0 13-31.

The control logic unit 704-1 also includes a secondary instructionregister (RSIR) which is loaded in parallel with the basic instructionregister at the start of processing an instruction. The contents of thesecondary instruction register RSIR 00-35, as previously mentioned, areapplied as inputs to the address preparation unit 704-3. Additionally, aportion of the contents of the secondary instruction register areapplied as inputs to the auxiliary arithmetic control unit 722 via thelines RSIR 1-9 and 24-35, and to the decimal unit 730 via the lines RSIR21-35.

The control store 704-2 as explained herein provides for an initialdecoding of program instruction op-codes and therefore is arranged toinclude a number of storage locations (1024), one for each possibleinstruction op-code.

As mentioned, signals applied to lines RBIR 18-27 are applied as inputsto control store 704-2. These signals select one of the possible 1024storage locations. The contents of the selected storage location areapplied to the lines CCSD0 13-31 and to CCSD0 00-12 as shown in FIG. 1.The signals supplied to lines CCSD0 00-12 correspond to address signalswhich are used to address the execution control unit 701 as explainedherein.

The execution unit 714 provides for instruction execution wherein unit714 performs arithmetic and/or shift operations upon operands selectedfrom the various inputs. The results of such operations are applied toselected outputs. The execution unit 714 receives data from a data inputbus which corresponds to lines RDI 00-35 which have as their source thecontrol logic unit 704-1. The contents of the accumulator and quotientregisters included within section 704-5 are applied to the executionunit 714 via the lines ZEB 00-35 as mentioned previously. The signalsapplied to the input bus lines ZD0 00-35 from the address preparationunit 704-3 are applied via switches included within the execution unit714 as output signals to the lines ZRESA 00-35 and ZRESB 00-35, as shownin FIG. 1. Additionally, execution unit 714 receives a set of scratchpad address signals from the auxiliary arithmetic and control unit 722applied via the lines ZRESPA 00-06. Additionally, the unit 722 alsoprovides shift information to the unit 714 via the lines ZRSC 00-35.

The character unit 720 is used to execute character type instructionswhich require such operations as translation and editing of data fields.As explained herein, these types of instructions are referred to asextended instruction set (EIS) instructions. Such instructions which thecharacter unit 720 executes include the move, scan, compare typeinstructions. Signals representative of operands are applied via linesZRESA 00-35. Information as to the type of character position within aword and the number of bits is applied to the character unit 720 via theinput lines ZDB 00-07.

Information representative of the results of certain data operations isapplied to the unit 722 via the lines ZOC 00-08. Such informationincludes exponent data and data in hexadecimal form. The character unit720 applies output operand data and control information to the unit 722,the unit 730 and the unit 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmeticoperations upon control information such as exponents used in floatingpoint operations, calculates operand lengths and pointers and generatescount information. The results of these operations are applied toexecution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-06 asmentioned previously. Information signals corresponding to characterssuch as 9-bit characters, 4-bit characters, decimal data converted frominput hexadecimal data, quotient information and sign information areapplied to section 704-5 via the lines RAAU 00-08.

As seen from FIG. 1, the unit 722 receives a number of inputs. Characterpointer information is applied via the lines ASFA 33-36. EIS numericscale factor information are applied to the unit 722 via the lines RSIR24-35. Other signals relating to fetching of specific instructions areapplied via the lines RSIR 01-09. Exponent signals for floating pointdata are applied to the unit 722 via the lines ZOC 00-08 while floatingpoint exponent data signals from unit 704-1 are applied via the linesRDI 00-08. Shift count information signals for certain instructions(e.g. binary shift instructions) are applied to the unit via the linesRDI 11-17. As concerns the input signals applied to the lines RCHU00-35, lines 24-35 apply signals corresponding to the length of EISinstruction fields while 18-23 apply address modification signals to theunit 722.

The multiply/divide unit 728 provides for high-speed execution ofmultiply and divide instructions. This unit may be consideredconventional in design and may take the form of the multiply unitdescribed in U.S. Pat. No. 4,041,292 which is assigned to the sameassignee as named herein. The unit 728 as seen from FIG. 1 receivesmultipler dividend and divisor input signals via the lines RCHU 00-35.The multiplicand input signal from register section 704-5 are appliedvia the lines ZAQ 00-35. The results of the calculations performed bythe unit 728 are applied as output signals to the lines ZMD 00-35.

The decimal unit 730 is operative under firmware control during theprocessing of decimal numeric instructions. The instruction format andits related descriptor words are described in greater detail withreference to FIG. 5. The instruction word and the descriptor wordinformation received by the decimal unit 730 via lines RSIR 21-35 andASFA 33-36. They condition the decimal unit 730 to receive the operanddescribed by the descriptor word from cache 750 via line ZDI 0-35. Thedecimal unit 730 strips the sign character and exponent characters fromthe operand word, packs the data into up to eight 4-bit characters perword, stores the data into 32-bit words, aligns and transfers the datawords to the execution unit 714 via lines RDOD 00-35, ZMD 00-35 and ZDO00-35. Data words stored in cache include up to four 9-bit characters ofeight 4-bit characters in a 36 bit word. The 9-bit character includesfive zone bits and four data bits. The zone bits are stripped from the9-bit character and the remaining data bits are packed into a 32-bitregister which may contain up to two cache data words made up of 9-bitcharacters or one cache data word made up of 4-bit characters. Thepacked data words of the operands are assembled in the execution unit714 and processed in accordance with the decimal numeric instruction.The operand representing the desired result of the numeric instructionis transferred to the decimal unit 730 via lines ZRESA 00-35 to thecharacter unit 720 and then to the decimal unit 730 via lines RCHU 4-35.There, the operand is processed in accordance with the coded informationin a descriptor word. The operand is unpacked, required signs andexponents added, via lines ZADSP 3-11, EBCIDIC or ASC11 zone charactersare added if 9-bit decimal characters are indicated by the descriptorword coded information, and stored back in cache 750 at an addressspecified by an address field in the descriptor word. The data is storedin cache 750 via lines RDOD 00-35, ZMD 00-35, ASFA 00-35 and RADO/ZADO00-35. The decimal unit 730 is under firmware control via lines MEM-DO88, 89, 94-97. PK-VCTR 0-3 signals signals from the decimal unit 730indicate to the execution address and branch circuit 701-1 statusinformation in response to firmware commands received by the decimalunit 730 via the lines MEM-DO 88, 89, 94-97. The PK-VCTR 0-3 signalsreceived by the execution address and branch 701-1 results in theexecution control store 701-2 branching to a particular microprogramsubroutine. U.S. Pat. No. 4,156,278 entitled "Multiple Control StoreMicroprogrammable Control Unit Including Multiple Function RegisterControl Field" described the branching logic associated with theexecution control store 701-2.

Data and control signals are transferred between cache 750 and an SIU100 via the data interfere line 600 and between cache 750 and theprocessor 700 via the lines of interface 604. Lastly, the cache unit 750receives address and data signals from the data and address outputcircuits 704-4 via the lines RADO/ZADO 00-35 and the lines ASFA 32-33.

Execution Unit 714--FIG. 2

The unit 714 includes as major units, addressable temporary registerbanks 714-10 and 714-12, an arithmetic logic unit (ALU) 714-20, ashifter 714-24 and a scratchpad memory 714-30. Additionally, the unit714 includes a number of multiposition data selector switches 714-15,714-17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to provideflexibility in selecting operands and output results.

In operation, the operands are selected via the ZOPA switch 714-15 andZOPB switch 714-17 from one of the registers of the banks 714-12 and714-10 or from other input lines such as ZEBo-35 or RDIo-35 as shown.The ALU 714-20 and shifter 714-24 performs operations upon the selectedoperands and the results are selected via the switches 714-24, 714-36and 714-38 to be applied to the output bus lines ZRESA 0-35 andZRESBO-35. Similarly, the contents of a scratchpad location selected viasignals applied to the ZRSPA 0-6 lines by the AACU unit 722 can be readout via the switches 714-34, 714-36 and 714-38.

The selected output results or other data are thereafter loaded intoother registers within processor 700 including the temporary registerbanks 714-12 and 714-10 or the scratchpad memory 714-30 of executionunit 714.

In greater detail, the sources of operands are identical for both theZOPA and ZOPB switches 714-15 and 714-17. The selection of switchposition for the ZOPA switch and ZOPB switch is under the control of themicroinstruction word. The ALU 714-20 performs logical, decimal andbinary operations upon the selected operand data under the control ofthe microinstruction word.

The shifter 714-25 is a combinational logic network used to align, shiftor rotate binary data under microprogram control. The input data signalsfrom the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed asbeing concatenated to form a single double word input. The shifter714-24 provides a 36-bit output shifted in accordance with the shiftcount. The ZSHFOP switch 714-28 is controlled by the microinstructionword while the shift count is established by the sequence controlconstant field of the microinstruction word which is appropriatelyselected via the auxiliary arithmetic control unit 722. For the purposesof the present invention, the ALU 714-20 and the shifter 714-24 may beconsidered conventional in design. The microinstruction fieldscontrolling the operation of the execution unit 714 are described inrelated U.S. Pat. No. 4,156,278 described supra.

The scratchpad memory 714-30 provides a working space for storingvarious data required for the execution of certain instructions as wellas various constants and descriptor values. For example, octal locations10-15 are used to store an edit instruction table value required forcarrying out edit operations. Writing into the scratchpad memory 714-30involves first loading the RSPB buffer register 714-32 with input dataapplied via the ZRESB switch 714-38. During a next cycle, the contentsof the register 714-32 are written into the location specified by thesignals applied to the ZRSPA 0-6 lines by the AACU unit 722. Writingtakes place when bit 22 of the microinstruction word (RSP field) isforced to a binary ONE.

As concerns the other switches, as mentioned, the results produced bythe unit 714 are provided via the ZALU switch 714-26, the BSPDI switch714-34, the ZRESA switch 714-36 and the ZRESB switch under microprogramcontrol. The ZALU and ZSPDI switches provide a first level of selectionto the ZRESA and ZRESB switches which provide a last level of selection.Since both the ZRESA and ZRESB switches have identical input sources,they can provide the same output data.

Operands from the decimal unit 730 are received via the ZDO 00-35 linesand stored in selected RTRL 0-3 registers 714-12 and RTRH registers714-10 as are described supra. Long operands are stored in scratchpadmemory 714-30. The resultant operand is read through the ZRESA switch714-36 into the RCHO register 720-10 of character unit 720 and to thedecimal unit 730 via the RCHO 0-35 line.

Decimal Unit 730--General Description--System

Referring to FIG. 3, the decimal unit 730 is operative under firmwarecontrol processing of decimal numeric instructions and receives datawords from cache 750 made up of 4-bit characters or 9-bit EBCDIC orASCII characters. The data word may contain a trailing sign or a leadingsign which may be part of an overpunched character and will also containan exponent if the data word is a part of a floating point operand.

The decimal unit 730 strips the sign and/or exponent from the data word,compresses the data words from 35bit words to 32-bit words, packs boththe 4-bit and 9-bit decimal digits into data words made up of 4-bitdecimal digits, and transfers the resulting 32-bit data words to theexecution unit 714 for processing as defined by the instruction.

The most significant and least significant words of the operand receivedfrom cache 750 may contain information which is not a part of theoperand. This rewrite information is stored in registers and added tothe most significant and least significant words of the operand ifrequired during the store operation.

The decimal unit 730 processes operands made up of decimal digits eitheras short operands or long operands. Short operands are 15 decimal digitslong or less. Long operands are from 16 to 64 decimal digits long.Operands having more than 64 decimal digits are not processed in thedecimal unit 730 but are processed by the firmware.

Short operands comprising 1 or 2 data words are transferred to temporaryregisters RTRL 0-3 714-12 and RTRH 4-7 714-10 in the execution unit 714.Long operands comprising from 3 to 8 words are transferred to thescratchpad memory 714-30 in the execution unit 714.

Decimal numeric instructions include an instruction word defining thearithmetic operation to be performed, a descriptor 1 word defining thecharacteristics of an operand 1, a descriptor 2 word defining thecharacteristics of an operand 2 and a descriptor 3 word defining thecharacteristics of a resultant operand 3. Some instructions usedescriptor 2 to define the characteristics of both operand 2 and operand3. The instruction and descriptor formats are shown in FIG. 5.

The decimal unit 730 under firmware control receives operands 1 and 2from cache 750, aligns them and transfers them to the execution unit714. Both operands are checked for an illegal sign or illegal digits.The resultant operand 3 is transferred from the execution unit 714 tothe decimal unit 730 where it is unpacked to 36-bit data words from32-bit data words, ASCII or EBCDIC zone characters are added for 9-bitwords. Exponent characters and signs are added if required. Operand 2 oroperand 3 rewrite information previously stored may be added. Theoperand is checked for zero/overflow conditions, is rounded or truncatedif required and stored back in cache 750.

Descriptors defining the operands are stored in the RSIR register (notshown in the drawings) of the control logic unit 714-1. The RSIR bitpositions 21 through 35 corresponding to the bit positions of thedescriptors of FIG. 5, are transferred to and stored in registers in thedecimal unit 730. The RSIR bit positions 17-20 are transferred to thedecimal unit as signals ASFA 33-36 which are also stored in a registerin the decimal unit 730.

As shown in FIG. 5, the descriptor fields are defined as follows:

ASFA 33 is the least significant bit of the address of the mostsignificant word of the operand indicating an odd or even word address.

ASFA 34-36 points to the digit position within the most significant wordof the high order character of the operand.

RSIR 21 indicates an operand of 4-bit characters if a ONE or 9-bitcharacters if a ZERO.

RSIR 22-23 defines the operand type and sign position.

00 Leading sign floating point or overpunched sign leading.

01 Leading sign scaled.

10 Trailing sign scaled

11 No sign scaled or overpunched sign trailing.

RSIR 24-29 indicates the scale factor, i.e., the position of the decimalpoint. A negative number moves the decimal point to left of the leastsignificant digit. A positive number moved the decimal point to theright of the least significant digit.

RSIR 30-35 indicates the number of characters in the operand. Charactersinclude decimal digits, sign characters and exponents.

The firmware controls the decimal unit with the signals RCSR 88-89,94-97. The signals are outputs from the execution control store 701-4.Except for the CLK, ZAM, MPYREG and DUCMD fields, the firmware word isdescribed in detail in the aforementioned application Ser. No. 853,944.

                                      TABLE 1                                     __________________________________________________________________________                          Logic Name of                                           RCSR Signals          Firmware                                                88, 89,                                                                             94, 95, 96, 97           Controlled                                     TYPE F                                                                              CLK, ZAM, MPYREG                                                                          Description  Signals                                        __________________________________________________________________________    1  0  0  0  0  0  Set FMYDV if DUCMD-200                                                        FP0P1D, otherwise                                                             NULL                                                        1  0  0  0  0  1  Select RESULT =                                                                            DUCMD-201                                                        ZERO indicator 1                                            1  0  0  0  1  0  Select 0P1 = ZERO,                                                                         DUCMD-202                                                        0P2 = ZERO indicators                                       1  0  0  0  1  1  Load STC MASK into                                                                         DUCMD-203                                                        RD0D                                                        1  0  0  1  0  0  Select DU OVERFLOW                                                                         DUCMD-204                                                        and TRUNCATION                                                                indicators                                                  1  0  0  1  0  1  Reset ZERO/OVER-                                                                           DUCMD-205                                                        FLOW CHECK logic                                            1  0  0  1  1  0  Set FCMPN if FP0P1D                                                                        DUCMD-206                                      1  0  0  1  1  1  Unused                                                      __________________________________________________________________________

    __________________________________________________________________________    RSCR                                                                          88,89 94,95,96,97                                                             TYPE F                                                                              DUCMD   DESCRIPTION     LOGIC NAME                                      __________________________________________________________________________    1  1  0 0 0 0 Set FMVN if FPφP1D,                                                                       DUCMD-300                                                     otherwise NULL                                                  1  1  0 0 0 1 Read OPERAND through DU                                                                       DUCMD-301                                       1  1  0 0 1 0 Force Load Complete                                                                           DUCMD-302                                                     Status                                                          1  1  0 0 1 1 Store Operand Thru DU                                                                         DUCMD-303                                       1  1  0 1 0 0 Check ZERO/OVERFLOW                                                                           DUCMD-304                                       1  1  0 1 0 1 Transfer Data from RCHO                                                                       DUCMD-305                                                     to RPK                                                          1  1  0 1 1 0 Load Rewrite Data                                                                             DUCMD-306                                       1  1  0 1 1 1 Load the DU Sign                                                                              DUCMD-307                                                     Register (RSGN)                                                 1  1  1 0 0 0 Load the DU Exponent                                                                          DUCMD-308                                                     Register (REXP)                                                 1  1  1 0 0 1 Put the Rounding Con-                                                                         DUCMD-309                                                     stant into RDφD                                             1  1  1 0 1 0 Put Operand Leading                                                                           DUCMD-310                                                     Zero Count into RDφD                                        1  1  1 0 1 1 Put Operand Word Count                                                                        DUCMD-311                                                     Into RDφD                                                   1  1  1 1 0 0 Unused                                                          1  1  1 1 0 1 Select Descriptor Vector                                                                      DUCMD-313                                                     Indicators                                                      1  1  1 1 1 0 Select Store Op Vector                                                                        DUCMD-314                                                     Indicators                                                      1  1  1 1 1 1 Select Long Op Vector                                                                         DUCMD-315                                                     Indicators                                                      __________________________________________________________________________

Note that the RSCR bit positions 88 and 89, the TYPE F field, define thefields identified by RSCR bit positions 94-97. If the TYPE F fieldcontains a "10" then microword fields CLK, ZAM, and MPYREG are selected.If the TYPE F field contains a "11" then microword field DUCMD isselected.

DUCMD 200 sets the FMYDV flag during a multiply or divide decimalinstruction.

DUCMD 201 selects the ADSZ conditional branch.

DUCMD 202 selects the RRLTRD conditional branch indicator if operand 1equal zero and selects the RREQRD conditional branch indicator ifoperand 2 equals zero.

DUCMD 203 transfers the RCHU 30-35 output signals storing the STC maskinto the RDOD register 730-154.

DUCMD 204 selects the RRLTRD conditional branch indicator for anoverflow and the RREQRD conditional branch indicator for a truncationoperation.

DUCMD 205 resets the RCRD and FDOFL flags.

DUCMD 206 sets the FCMPN flag if the FPOP1D flag is at logical ONE.

DUCMD 300 sets the FMV flag if the FPOP1D flag is at logical ONE.

DUCMD 301 starts the operand load operation in the decimal unit 730.

DUCMD 302 forces completion of the load operation by setting theFLDCOMPL and the FRDP1 flags.

DUCMD 303 starts the store result through the decimal unit 730 bysetting the FOPSTR and FMSDRN flags.

DUCMD 304 sets the FCZO flag for a check zero/overflow of the wordstored in the RCHO register 720-10.

DUCMD 305 sets the FCZO and FRPK flags.

DUCMD 306 sets the FLDREWR flag and selects the RREQRD condition branchindicator for a truncation operation.

DUCMD 307 conditions the loading of the sign register RSGN 730-134.

DUCMD 308 conditions the loading of the exponent register REXP 730-138.Also conditions the loading of the RSF3 scale factor register ofregister bank 730-4 during a floating point FPOP3 cycle.

DUCMD 309 controls the loading of the rounding constant stored in theZPK switch 730-150 into the proper character position of the RDODregister 730-154 and sets the FRCMD flag.

DUCMD 310 controls the loading of the operand leading zero count intothe RDOD register 730-154.

DUCMD 311 controls the loading of the operand word count into the RDODregister 730-154.

DUCMD 312 unused.

DUCMD 313 selects the descriptor 1 vector and descriptor 2 vectorindicators and sets the FDVC1 flag.

DUCMD 314 resets the FCRD flag and selects the store vector indicators.

DUCMD 315 selects the long input vector indicators.

The Decimal Unit 730 responds to the firmware requests with the PK VCTR0-3 signals indicated below.

                  TABLE 2                                                         ______________________________________                                        VECTOR BRANCH DATA                                                            ______________________________________                                        PK-VCTR                                                                       0 1 2 3                                                                                TYPE - LENGTH                                                        0 0 0 0 Short Operand and 4-bit data                                          0 1 0 0 Short Operand and 9-bit data                                          1 0 0 0 Short Operand and (4 or 9 bit data)                                           and overpunched sign                                                  1 1 0 0 Long Operand                                                                   DESCRIPTOR 1 VECTOR                                                  0 0 0 0 Execute Descriptor 2 vector                                           0 1 0 0 Descriptor 1 = floating point                                         1 0 0 0 Descriptor 1 = overpunched leading sign, scaled                       1 1 0 0 Descriptor 1 = overpunched trailing sign, scaled                               DESCRIPTOR 2 VECTOR                                                  0 0 0 0 Descriptor 2 ≠ floating point or overpunched                            sign                                                                  0 1 0 0 Descriptor 2 = floating point                                         1 0 0 0 Descriptor 2 = overpunched leading sign, scaled                       1 1 0 0 Descriptor 2 = overpunched trailing sign, scaled                               STORE VECTOR                                                         0 0 0 0 Check for RESULT = ZERO, OVERFLOW                                     0 1 0 0 Floating point result - Check for RESULT = 0,                                 Overflow                                                              1 0 0 0 Overpunched leading sign output - check for                                   RESULT = 0, Overflow                                                  1 1 0 0 Overpunched trailing sign output - Check for                                  RESULT = 0, Overflow                                                           LONG - INPUT                                                         0 0 0 0 Both operands scaled and adjusted length                                      descriptor 1 ≦63 and adjusted length descriptor                        2 ≦63 and overpunched sign                                     0 1 0 0 Both operands scaled and adjusted length                                      descriptor 1 ≦63 and adjusted length descriptor                        2 ≦63 and overpunched sign                                     1 0 0 0 Both operands scaled and adjusted length                                      descriptor 1 >63 or adjusted length descriptor                                2 >63                                                                 1 1 0 0 Execute descriptor 1 and descriptor 2 vectors                         ______________________________________                                        PREDICTED NUMBER OF CYCLES OF DELAY FOR                                       PROCESSING DESCRIPTOR 1 or DESCRIPTOR 2                                       OPERANDS                                                                                  WORDS         CYCLES                                              PK-VCTR     OF            OF                                                  0 1 2 3     DATA          DELAY                                               ______________________________________                                        0 0 0 0     1             0                                                   0 0 0 1     2             0                                                   0 0 1 0     1             1                                                   0 0 1 1     2             1                                                   0 1 0 0     1             2                                                   0 1 0 1     2             2                                                   ______________________________________                                    

The following Boolean expressions show the firmware selection of thevector branch data:

    [1PKVCTR=FDUACT (DUDMD 315+DUCMD 313·FDCV1+FRDP1(DUCMD 313·DUCMD 314·DUCMD 315))

    [2PKVCTR=FDUACT (DUCMD 314+DUCMD 315+DUCMD 301+DUCMD 313·FRDP1)

    [4PKVCTR=FDUACT (DUCMD 313+DUCMD 314+DUCMD 315)

[FKVCTR=1 selects the type length vector which indicates to the firmwarewhether the operand is a short or long operand. 4 bit characters or 9bit characters and if a short operand whether there is an overpunchedsign in the descriptor 1 or descriptor 2 operands.

[PKVCTR=2 or 3 selects for short operands the number of cycles of delayneeded after the first read command is sent to cache 750 to the firstdata word being sent to the execution unit 714. This predictionsimplifies the firmware processing of short operands.

[PKVCTR=4 selects the descriptor 1 vector which defines descriptor 1 asa floating point operand, an overpunched leading or trailing sign scaledoperand or indicates to the firmware to execute the descriptor 2 vector.

[PKVCTR=5 selects the descriptor 2 vector which defines descriptor 2 asa floating point or scaled operand with overpunched leading or trailingsign.

[PKVCTR=6 selects the store vector which indicates to the firmware tospecific check for resulting operand equal to zero.

[PKVCTR=7 selects the long-input vector and indicates to the firmwarethe comparison between the operand lengths and 63 for scaled operands.The vector also indicates to the firmware to execute the descriptor 1and descriptor 2 vectors.

The decimal unit 730 supplies a number of conditional branch indicatorsto the execute address and branch circuits logic 701-1.

    ______________________________________                                        CONDITIONAL BRANCH INDICATORS                                                 Name                  Source                                                  ______________________________________                                        START-WRT             RRLTRD                                                  SEND-DATA             RREQRD                                                  OP1 = ZERO            RRLTRD                                                  OP2 = ZERO            RREQRD                                                  OVERFLOW              RRLTRD                                                  TRUNCATION            RREQRD                                                  RESULT = ZERO         ADSZ                                                    DATA-AVA              ADSZ                                                    CK-STR-VECT           ZAMO                                                    ______________________________________                                    

The RRLTRD signal is generated:

1. during a DUCMD 202 command when the FOP1Z flag is set indicating thatoperand 1 is zero.

2. during a DUCMD 204 command when the FDOFL flag is set indicating thatthere was an operand overflow.

3. during a first write operation to indicate to the firmware to sentwrite commands to cache 750.

The RREQRD signal is generated:

1. during a DUCMD 204 or DUCMD 306 command with the truncation signal atlogical 1 indicating that least significant digits of an operand will belost.

2. during a DUCMD 202 command when the FOP2Z flag is set indicatingoperand 2 is zero.

3. during a send data operation to indicate to the firmware to transferdata to the decimal unit 730 from the execution unit 714.

The ADSZ signal is generated:

1. during a DUCMD 201 command when the operand is equal to zero.

2. when data is not available except during a DUCMD 201 command.

The ZAMO signal is generated to indicate a check store vector functionsuch as floating point, overpunched character, overflow, result=0operand.

The conditional branch indicators are called for by the firmware andresults in an execution control store 701-2 branch.

Description of decimal unit status flags including the booleanexpressions for setting and resetting the flags are:

F3DESC Set for the processing of operand 3 which is defined by eitherdescriptor 2 or descriptor 3. The boolean expression is: F3DESC SET:(FPOP·RDESC0·RDESC1) F3DESC RESET: (FPOA)

FALT Set during the store operation on alternate cycles. The decimalunit prepares a word for the RDOD register 730-154 on one cycle andtransfers the word to the Execution Unit 714 on the next cycle. FALT setenables the storing of a word in the RDOD register. The booleanexpression is:

FALT SET: ((DUCMD 303+FOPSTR)·FALT·FPOA)

FALT RESET: (FOPSTR·FALT+FPOA)

FCMPN Set for a DUCMD 206 firmware command for a compare numericinstruction. The boolean expression is:

FCMPN SET: (FPOPlD·DUCMD 206)

FCMPN RESET: (FPOA)

FCPCO Set when loading or storing 9-bit data words from odd addresses inCache 750. The boolean expression is:

FCPCO SET: ((ZCPA0·(FDUACT·FRDP1+SFOP2LD+FLDOMPL·(DUCMD303+FOPSTR))+FCPCO·(FOP1LD·SFOP2LD+FOP2LD)·(FDID+FDFD)+FCPCO·(DUCMD303+FOPSTR)·[RDOD)·FPOA)

FCPCO RESET: (ZCPA0·(FDUACT·FRDP1+SFOP2LD+FLDCOMPL ·DUCMD303+FOPSTR))+FCPCO ·(FOP1LD·SFOP2LD+FOP2LD) ·(FDID+FDFD)+FCPCO ·(DUCMD303+FOPSTR)·[$RDOD+FPOA)

FCRP1 Set during an operand load operation when one of the operands islong. This flag lets the second load DU operand command (DUCMD 301)start a load process. A long operand causes the decimal unit to cancelthe first load DU operand command (DUCMD 301) to enable the firmware toget set up to process a long operand. The firmware always assumes ashort operand operation. The boolean expression is:

FCRP1 SET: ((DUCMD 301·FRDP1·(D1EQOVP+D2EQOVP+LONG))·FPOA)

FCRP1 RESET: (FPOA)

FCRD Set by a DUCMD 305 firmware command or an FCZO flag on for a checkzero/overflow operation and reset by a DUCMD 205 or 314 command. Remainsset for the entire operation processing. The boolean expression is:

FCRD SET: ((DUCMD 305+FCZ0)·FPOA)

FCRD RESET: (DUCMD 314+DUCMD 205+FPOA)

FCZ0 Set by a DUCMD 304 or 305 firmware command for a checkzero/overflow of the word stored in the RCHO register 720-10. Theboolean expression is:

FCZ0 SET: ((DUCMD 305+DUCMD 304))·FPOA)

FCZ0 RESET: (SFCZ0+FPOA)

FDADIS Set for 9-bit decimal digit operand loads on alternate cycles toallow two 4 digit words to be received from cache 750 and stored in theRDOD register 730-154 as one 8 digit word. The boolean expression is:

FDADIS SET: ((ZTNSA0·FRDP2+ZTNSB0 ·FRDP2)·DATA-AV·FPOA·SFOP2LD)

FDADIS RESET: (SFDADIS·([$RDI-PC+SFDFD+FDFD·RFDFD)+SFOP2LD)

FDATA-AV Is set to load the RDOD register 730-154 by controlling thestrobe signal [$RDODA. The boolean expression is:

FDATA-AV SET: (DATA-AV·FPOA)

FDATA-AV RESET: (SFDATA-AV+FPOA)

FDFD Is set during a load operation to indicate that the completeoperand has been received from cache 750 by the decimal unit 730. Theboolean expression is:

FDFD SET: (DFCO·FDID·(RFDFD)·FPOA·(FOP1LD ·SFOP2LD+FOP2LD))

FDFD RESET: (FPOA+DFCO·FDID·DTECO·[$RDODA+DFCO·FDID·FDTED+DTECO·[$RDODA·FDFD)

FDID Set when operand data is loaded into the RDID registers 730-158.The boolean expression is:

FDID SET: ([$RDI-PC·FLDREWR·FRDP1)

FDID RESET: (SFDID)

FDOFL Set when an operand overflow is detected during a checkzero/overflow operation and reset by a DUCMD 205. The boolean expressionis:

FDOFL SET: ((DUCMD 305+FCZO)·DOFL·FPOA)

FDOFL RESET: (DUCMD 205+FPOA)

FDTED Set when all of the decimal digits of the operand were sent to theexecution unit 714 but not all of the operand information has beenreceived by the decimal unit; exponent or sign information for example.The boolean expression is:

FDTED SET: (DTECO·[$RDODA·(RFDFD)·FPOA ·(FOP1LD·SFOP2LD+FOP2LD))

FDTED RESET: (FRDFD)

FDUACT Set during an FPOP control logic unit 704-1 cycle to indicate adecimal unit 730 operation. The boolean expression is:

FDUACT SET: (FPOP)

FDUACT RESET: (FPOA)

FDVC1 Is set when the firmware sends a DUCMD 313 for descriptor 1information so that descriptor 2 information is sent on the next DUCMD313. The boolean expression is:

FDVC1 SET: (DUCMD 313·FPOA)

FDVC1 RESET: (FPOA)

FDZERO Is set if the operand check with the check zero/overflow commandsDUCMD 304 or 305 equal to zero. The boolean expression is:

FDZERO SET: ((DUCMD 305+FCZO)·DZERO·FPOA)

FDZERO RESET: (FPOA+(DUCMD 305+FCZO) ·DZERO·FCRD)

FFDI Is set when the first word of the operand from cache 750 is loadedinto the decimal unit. The boolean expression is:

FFDI SET: ((FDID·DFCO·(FOP1LD+FOP2LD))·FPOA)

FFDI RESET: (SFOP2LD+FPOA)

FFDO Is set when the first word of the operand is stored in the RDODregister 730-154 prior to being transferred to the execution unit 714.The boolean expression is:

FFDO SET: (([$RDODA & (FOP1LD+FOP2LD)·DTECO)·FPOA)

FFDO RESET: (SFOP2LD+FPOA)

FFOSD Is set when the first data word to be stored in cache 750 isloaded into the RDOD register 730-154. The boolean expression is:

FFOSD SET: ((FOPSTR+DUCMD 303)·[$RDODA·FPOA)

FFOSD RESET: (FPOA)

FILLDIG Is set when an illegal digit or illegal length is received bythe decimal unit 730. It signals a fault to the system and is reset onecycle later by the FLDGR flag. The boolean expression is:

FILLDIG SET: (([$RDODA·(FOP1LD+FOP2LD) ·DZIDEQID+ILLEGALLENGTH·(SFOP1LD+FCZO))·(FLDGR+FPOA))

FILLDIG RESET: (FLDGR+FPOA)

FLDCOMPL Is set when both operands have been transferred to theexecution unit 714. The boolean expression is:

FLDCOMPL SET: (((FOP1LD·FMVN+FOP2LD·FMVN)·(DFCO·FDID·DTECO·[$RDODA+DFCO·FDID·FDTED+DTECO·[$RDODA·FDFD)+DUCMD302)·FPOA)

FLDCOMPL RESET: (FPOA)

FLDGR Is set at the same time as the FILLDIG flag, i.e., when an illegaldigit or illegal length is received in the decimal unit 730. It resetsthe FILLDIG after one cycle. The boolean expression is:

FLDGR SET:(([$RDODA·(FOP1LD+FOP2LD)·DZIDEQID+ILLEGALLENGTH.multidot.(SFOP1LD+FCZO))·FOPA)

FLDGR RESET: (FPOA)

FLDREWR Is set from the firmware by a DUCMD 306 load rewrite data signalto start the sequence for storing the first or last words defined bydescriptor 3 in the REWR O-3 register bank 730-177. The booleanexpression is:

FLDREWR SET: (DUCMD 306)

FLDREWR RESET: (DUCMD 306)

FLDREWRH Is set one cycle after the FLDREWR flag is set to strobe thefirst or last word into the REWR2 or REWR3 register respectively of theREWR 0-3 register 730-177 during a descriptor 2 store operation. Theboolean expression is:

FLDREWRH SET: (FLDREWR)

FLDREWRH RESET: (FLDREWR)

FMSDRGTE Is set during a store operation on a DUCMD 303 firmware commandif word count in the RRWC register is greater than or equal to the wordcount in the RWPC register at the time the DUCMD 303 is used. Theboolean expression is:

FMSDRGTE SET: (DMSDRGTE·DUCMD 303)·FALT·(DUCMD 303·RRWC0+FMSDRN)·FPOA

FMSDRGTE RESET: (FPOA)

FMSDRN Sets on the DUCMD 303 firmware command for a long operand storeif the word count in the RRWC register is negative initially. Theboolean expression is:

FMSDRN SET: (DUCMD 303·RRWC0·FPOA)

FMSDRN RESET: (FPOA)

FMSEQ Sets during a long operand store sequence when the word count inthe RRWC register equals the word count in the RWPC register. Theboolean expression is:

FMSEQ SET:(DMSEQ·(FSWRT·DMSDRGTE+FSWRT·(ZTNSA0+ZTNSA0.multidot.FCPC0))·(DUCMD303+FOPSTR)·FALT·(DUCMD 303·RRWC0+FMSDRN)·FPOA)

FMSEQ RESET: (FPOA)

FMVN Is set for a move numeric instruction. The boolean expression is:

FMVN SET: (DUCMD 300·FPOP1D)

FMVN RESET: (FPOA)

FMYDV Is set for multiply and divide instructions. This flag suppressesthe scale factor alignment and right justifies the operands on a loadoperation. The boolean expression is:

FMYDV SET: (DUCMD 200·FPOP1D)

FMYDV RESET: (FPOA)

FOP1LD Is set for the operand one load operation. The boolean expressionis:

FOP1LD SET: (DUCMD 301·FRDP1·FPOA·(D1EQOVP·D]EQOVP.multidot.LONG+FCRP1))

FOP1LD RESET:(FPOA+FOP1LD·DFCO·DTECO·FDID·[$RDODA+FOP1LD·DFCO·FDID·FDTED+FOP1LD·DTECO.multidot.[$RDODA·FDFD)

FOP1Z Is set if operand 1 equals zero. The boolean expression is:

FOP1Z SET: ([$RDODA·FOP1LD·DZIDEQZ·FPOA)

FOP1Z RESET: (FPOA)

FOPSTR Is set by the DUCMD 303 store operand through decimal unit 730firmware command. The boolean expression is:

FOPSTR SET: (DUCMD 303·FPOA)

FOPSTR RESET: (FPOA)

FOP2F Is set for an operand 2 load and the first data word is receivedin the FDID register 730-155. The boolean expression is:

FOP2F SET: (FDID·FOP2LD·FPOA·DFCO)

FOP2F RESET: (FPOA+DFCO·FDID)

FOP2LD Is set for the operand 2 load operation. The boolean expressionis:

FOP2LD SET: ((FOP1LD·FMVN·(DUCMD301+FRDP2)·(DFCO·FDID·DTECO·[$RDODA+DFCO·FDID·FDTED+DTECO·[$RDODA·FDFD)+FOP1LD·FMVN·DUCMD301·FRDP1)·FPOA)

FOP2LD RESET:(FPOA+FOP2LD·(DFCO·FDID·DTECO·[$RDODA+DFCO·FDID·FDTED+DTECO·[$RDODA·FDFD))

FOP2S Is set on an operand 2 load operation when the second word isstored in the RDID register 730-158. The boolean expression is:

FOP2S SET: (FOP2F·FDID·FPOA)

FOP2S RESET: (FPOA)

FOP2Z Is set if operand 2 is equal to zero. The boolean expression is:

FOP2Z SET: ([$RDODA·FOP2LD·DZIDEQZ·FPOA)

FOP2Z RESET: (FPOA)

FPFL Is set if operand 1 or operand 2 are specified as floating point.The boolean expression is:

FPFL SET: ((D1EQFLT+D2EQFLP) FOP1LD·FPOA))

FPFL RESET: (FPOA)

FRCMD Is set by a DUCMD 309 firmware command to read the roundingconstant into the RDOD register 730-154. The boolean expression is:

FRCMD SET: (DUCMD 309·FPOA)

FRCMD RESET: (FPOA)

FRDIDH Is set to indicate that the requested information is not storedin cache 750 and cache must request it of backing store. When the datais received in cache and sent to the decimal unit 730, the FRDIDH flaggates the recovery signal to strobe the data into the RDID register730-158. The boolean expression is:

FRDIDH SET: ([$RDI-PC)

FRDIDH RESET: (FRDIDH)

FRDP1 Is set by DUCMD 301 or DUCMD 302 firmware commands to indicatethat the command for reading the first operand has been issued to thedecimal unit 730. The boolean expression is:

FRDP1 SET: ((DUCMD 301·(D1EQOVP·D2EQOVP·LONG+FCRP1)+DUCMD 302)·FPOA)

FRDP1 RESET: (FPOA)

FRDP2 Set by a DUCMD 301 firmware command when the FRDP1 flag is set toindicate that the command for reading the second operand has been issuedto the decimal unit 730. The boolean expression is:

FRDP2 SET: (DUCMD 301·FRDP1·FPOA)

FRDP2 RESET: (FPOA)

FREWR Is set by the FLDREWRH flag in the cycle following the setting ofthe FLDREWRH flag. The flag is used to force the rewrite data to be readfrom REWR2 and REWR3 during the operand store process. The booleanexpression is:

FREWR SET: (FLDREWRH·FPOA)

FREWR RESET: (FPOA)

FREWR2 Is set by the FREWR and FLDREWRH flags both on. It causes theREWR3 register to be used to provide rewrite data for the last word ofoperand 3. The boolean expression is:

FREWR2 SET: (FLDREWRH·FREWR·FPOA)

FREWR2 RESET: (FPOA)

F3DESC Is set for the descriptor 3 operation. The boolean expression is:

F3DESC SET: (FPOP·RDESC0·RDESC1)

F3DESC RESET: (FPOA)

FPOP3D Is set for the cycle following FPOP3 cycle of the control logicunit 704-1. The boolean expression is:

FPOP3D SET: (FPOP·RDESC0·RDESC1)

FPOP3D RESET: (FPOA+FPOP3D·(DUCMD 305+FCZ0))

FPTL Is set for the condition that the adjusted length, length plusscale factor difference is greater than 63 characters. The booleanexpression is:

FPTL SET: (ALNSLTE63·FOP1LD·FPOA)

FPTL RESET: (FPOA)

FRPK Is set on a DUCMD 305 transfer data from RCHO to RPK firmwarecommand and is used for the short operation store. The booleanexpression is:

FRPK SET: (DUCMD 305·D1EQFLP·FPOA)

FRPK RESET: (FPOA+DUCMD 205)

FSND Is set when the SEND DATA bit is forced to a ONE. SEND DATAindicates to the firmware to load a new word into the RCHO register720-10 during a long operand store. The FSND flag strobes the previousword stored in the RCHO register into the RPK register 730-162. Theboolean expression is:

FSND SET: (FALT·SEND-DATA·FPOA)

FSND RESET: (FALT·SEND-DATA+FPOA)

FSSFD Is set when the scale factor difference is negative. The booleanexpression is:

FSSFD SET: (ASF2·FDUACT·FRDP1)

FSSFD RESET: (ASF2·FDUACT·FRDP1+FPOA)

FSWRT Is set when the STRT-WRT signal to the firmware is forced to ONE.STRT-WRT enables the firmware to start issuing write commands to thecache 750 during the long operand store procedure. FSWRT informs the DUhardware control that the firmware is issuing write commands. Theboolean expression is:

FSWRT SET: (FALT·STRT-WRT·(DUCMD 303+FOPSTR)·FPOA)

FSWRT RESET: (FPOA)

FPOP1D Is set for the cycle following FPOP1 cycle of the control logicunit 704-1. The boolean expression is:

FPOP1D SET: (FPOP·RDESC0·FDESC1)

FPOP1D RESET: (SFPOP1D)

FTDBO Are set as a 2-bit counter to count down

FTDB1 the number of cycles of delay for strobing the operand word intothe RDOD register 730-154 for transfer to the execution unit 714. Theboolean expression is:

FTDBO SET: (TDBO·DUCMD 301·FPOA)

FTDBO RESET: (TDBO·DUCMD 301+(FOP1LD+FOP2LD)·DUCMD 301·[$RDI-PC+FPOA)

FTDB1 SET: ((TDB1·DUCMD 301+FTDBO ·(FOP1LD·FOP2LD)·DUCMD 301·[$RDI-PC)·FPOA)

FTDB1 RESET: (TDB1·DUCMD 301+FTDB1·(FOP1LD+FOP2LD)·DUCMD301·[$RDI-PC+FPOA)

FZCF Is set during the load operand procedure when the first non zerocharacter is detected in the input data. It indicates the end of thenumber of leading zeros in the operand.

FZCF SET: ([$RDODA·(FOP1LD+FOP2LD)·LZC0·FPOA))

FZCF RESET: (SFOP2LD+FPOA))

The following are the boolean expressions for functions not previouslydescribed:

SFCZO=(DUCMD 305+DUCMD 304)·FPOA

SFDADIS=(ZTNSA0·FRDP2+ZTNSB0·FRDP2)·DATA-AV.multidot.FPOA·SFOP2LD

SFDFD=DFCO·FDID·(RFDFD)·FPOA

SFDATA-AV=DATA-AV·FPOA

[$RDI-PC=ENABIZ+FTRF+FMT·(SRADO1+(RDIN.EQ.(1-11))+TYPE·(MISREG.EQ.4)+TYPD·(IBUF.EQ.3))+FMT·((IBPIPE.EQ.1).multidot.FE12+TYPBD(2)·(MSKD.NEQ.0)+TYPBD (3)·STL)+FREQCA·(RMEM.EQ.(8-10))+FREQDI+FDIDBL

SFDID=[$RDI-PC·FLDREWR·FRDP1

DOFL indicates an overflow condition

DZIDEQID=(ZID4·(ZID5+ZID6))+(ZID8·(ZID9+ZID10))+(ZID12.multidot.(ZID13+ZID14))+(ZID16·(ZID17+ZID18))+(ZID20·(ZID21+ZID22))+(ZID24·(ZID25+ZID26))+(ZID28·(ZID29+ZID30))+(ZID32.multidot.(ZID33+ZID34))

ILLEGALLENGTH=ALNDA0+ALNDB0+ALNDAZ+ALNDBZ

DZERO indicates that the operand word contains all zeros.

Decimal Unit - Logic

The scale factors for operands 1, 2 and 3 are received in the decimalunit 730 through a 4 position switch ZSFN 730-2 over signal lines RSIR24-29 from the control logic unit 704-1 and are stored in registersRSF0, RSF1, RSF2 respectively of register bank 730-4. ZADSP 3-11 signallines apply the scale factor to position 0 of the switch when the scalefactor is calculated by the firmware. ALNDA signal lines apply theadjusted length of operands to position 2 of the switch during afloating point operation. The AEDC and ZEDC signals are applied toposition 3 of the switch to store the number of effective digits duringa floating point operation. This is described in greater detail as partof the store operation description.

Control signals [1ZSFN and [2ZSFN select the switch 730-2 positions. Theboolean expressions are

[1ZSFN=((F3DESC+FMVN)·FLDCOMPL·FPOP·(D1EQFLP+DUCMD 305+FCZ0))

[2ZSFN=((F3DESC+FMVN)·FLDCOMPL·FPOP·D1EQFLP)

For non floating point operands the operand 2 scale factor is selectedby the RSF1 position of a ZSFB switch 730-8 and is applied to an inputof an ASF adder 730-10 where the operand 2 scale factor is subtractedfrom the operand 1 scale factor selected by the RSF0 position of a ZSFAswitch 730-6. If the operand 1 scale factor is larger than the operand 2scale factor then the signals ASF0-9 represent a positive number and bitposition ASF2 is a logical ZERO. If the operand 2 scale factor islarger, then the signals ASF0-9 represent a negative number and bitposition ASF2 is a logical ONE.

The length or number of numeric characters for operands 1, 2 and 3 isreceived over signal lines RSIR 30-35 from the control logic unit 704-1and are stored in registers RLND0, RLND1 and RLND2 respectively of aregister bank 730-12. An ALNDA adder 730-18 and an ALNDB adder 730-20calculate the number of decimal digits in operands 1 and 2 respectively.This is accomplished by subtracting the number of non digit charactersin the operand such as sign and exponent from the length. The output ofa decode logic 730-38 and a decode logic 730-40 is applied to addersALNDA 730-18 and ALNDB 730-20 respectively to adjust the operand 1 andoperand 2 lengths.

The sign and decimal type for operands 1, 2 and 3 are received oversignal lines RSIR 21-23 from the control logic unit 704-1 and are loadedinto registers RTNS0, RTNS1 and RTNS2 respectively of register bank730-32. A ZTNSA switch 730-36 selects the operand 1 sign and decimaltype stored in register RTNS0 and applies it to the decode logic 730-38.A scaled unsigned operand results in a ZERO output, a scaled signedoperand results in a ONE output, a floating point operand having 9-bitdecimal digits results in a TWO output and a floating point operandhaving 4-bit decimal digits results in a THREE output from decode logic730-38 respectively. The output value is subtracted from the operand 1length in the ALNDA adder 730-18 to give as an output, signals ALNDA 0-6which indicate the number of decimal digits in operand 1. The number ofdecimal digits in operand 2 indicated by signals ALNDB 0-6 arecalculated in a similar manner.

Signals DBITX and DBITZ at logical ONE indicates that a binary ONE issubtracted from the ALNDA adder 730-18 and the ALNDB adder 730-20respectively. The boolean expressions are

DBITX=((ZTNSA1·ZTNSA2)+(ZTNSA0·ZTNSA1·ZTNSA2))

DBITZ=((ZTNSB1·ZTNSB2)+(ZTNSB0·ZTNSB1·ZTNSB2))

Signals D1EQFLP and D2EQFLP at logical ONE indicates that a binary TWOis subtracted from the ALNDA adder 730-18 and the ALNDB adder 730-20respectively. The boolean expressions are

D1EQFLP=(ZTNSA1·ZTNSA2·(ZTNSA0+ROP1))

D2EQFLP=(ZTNSB1·ZTNSB2·(ZTNSB0+ROP1))

ROP1 indicates an overpunched sign instruction.

A ZALND switch 730-22 selects the adjusted length of the operand withthe larger scale factor and applies the output to an ALNS adder 730-24which adds to it the absolute value of the scale factor ASF 0-9 outputof the ASF 730-10 adder. Bit position ASF2 selects the operand with thelarger scale factor. Bit position ASF2 at a logical ONE indicates thatthe operand 2 scale factor is larger.

The output of a ZLNADJ switch 730-26 applies the adjusted length to anARWC counter 730-60 and an ACPR counter 730-62. The inputs to the ZLNADJswitch 730-26 are described below.

If the operand 1 scale factor is larger, then the switch selects theALNS 0-9 input signals for operand 1 and the ALNDB input signals foroperand 2. If the operand 2 scale factor is larger, then the switchselects the ALNDA 0-6 input signals for operand 1 and the ALNS inputsignals for operand 2. A floating point operand or a multiply or divideinstruction does not require a scale factor alignment, therefore, theALNDA 0-6 and ALNDB 0-6 input signals are selected for operand 1 andoperand 2 respectively. The RLZC1 input signals are selected during afloating point store operand and provide the number of leading zeros inthe operand.

Control signals 41ZLNADJ and 42ZLNADJ select one of four positions ofZLNADJ switch 730-26. The boolean expressions are

[1ZLNADJ=(FLDCOMPL·FRDP1·(FSSFD+FMYDV+D1EQFLP++D2EQFLP+ALNS2)+FLDCOMPL(F3DESC+FMVN)·D1EQFLP·FDOFL)

[2ZLNADJ=(FDOACT·FRDP1·ASF2+FRDP1·FSSFD).multidot.FMYDV·D1EQFLP·D2EQFLP+ALNS2·FLDCOMPL+FLDCOMPL.multidot.(F3DESC+FMVN)·D1EQFLP+D1EQFLP·FDOFL)

If the outputs of the ALNDA adder 730-18, the ALNDB adder 730-20 and theALNS adder 730-24 are all 15 decimal digits or less, this indicates thatthe non floating point decimal instructions are executed in the shortoperand mode. This mode provides for increased system throughput inprocessing decimal instructions over the prior art, since much of theoperand manipulation is done using logic performing many of the operandsetup functions in parallel. The prior art performed many of thefunctions serially. The boolean expression for the short operand is asfollows:

Short=(ALNDA1·ALNDA2)(ALNDB1·ALNDB2)(ALNS3·ALNS4·ALNS5+FMYDV)(D1EQFLP+D2EQFLP)

Note that the scale factor adjustment is not implemented for themultiply or divide instructions.

The ARWC adder 730-60 calculates the number of words to be transferredto the execution unit 714 for both short and long operands. The signal[ONE/ARWCB is applied to the minus input to adder ARWC 730-60 and, whenat logical ONE, is subtracted from the adjusted length ZLNADJ 0-9 for aload operation. This assures that if the adjusted length as indicated bythe ZLNADJ 0-9 signals was 8-decimal digits, i.e. the ZLNADJ6 signal wasa ONE, then subtracting ONE would make bit position ARWC6 a ZERO and 8decimal digits will be loaded into the first word. Discarding bitpositions ARWC 7-9 leaves bit position ARWC6 as indicating the number ofwords for the short operand. A ONE in bit position ARWC6 indicates ashort operand of 2 words and a ZERO indicates a short operand of oneword. The boolean expression for control signal [ONE/ARWCB

[ONE/ARWCB=(FLDCOMPL+(ZTNSA1(ROP1+ZTNSA0+ZTNSA2))+(FRPK·ZLNADJ7.multidot.ZLNADJ8·ZLNADJ9·FLDCOMPL))

The ARWC 0-6 output signals indicating the number of words in theoperand is available to the firmware when the execution control store701-4 sends a firmware word which is decoded in the decimal unit 730 asa DUCMD 311 "Put Operand Word Count into RDOD" signal and makes the wordcount available through a ZLZC switch 730-76, position 3 of a ZID switch730-150, position 0 of a ZDOD switch 730-152 to a RDOD register 730-154from which it is transferred to the execution unit 714.

The ACPR adder 730-62 subtracts the adjusted length in decimal digitsdecoded by the ZLNADJ 0-9 signals from decimal 64. The quantity 64 isthe maximum number of digits in an operand that is processed by thedecimal unit 730. The resulting output signals ACPR 3-9 indicate thenumber of zero digits to the left of the high order digit position for a64 decimal digit operand. This value is stored in an RLMP register730-102. Bit positions RLMP 4-6 store a binary code indicating thenumber of high order positions in the first word of the operand receivedby the decimal unit 730 to be forced to ZERO. The RLMP 4-6 signals areapplied to a ZIDMU shifter 730-130. The number of high order digits tothe left of the most significant digit position to be forced to ZERO isindicated by the number of successive signals starting with the ZIDMU 0signal which are forced to ZERO. The ZIDMU 0-7 signals are applied to a[EZID logic control 730-132. The output signals [EZID 0-7 output signalssuppress the ZID switch 730-150 in zero to the left positions andenables the digit positions of a ZID switch 730-150 starting with themost significant digit position. The portion of the RLMP register730-102 storing the RLMP 0-3 bit positions has the capability of beingincremented for every operand word received by the decimal unit 730 bythe [CNTUP-RLMPU signal. The boolean equation is

[CNTUPRLMPU=((FOP1LD+FOP2LD)·[$RDODA·SFOP2LD)

The boolean expression for the signal [ONE/ACPNBB is:

[ONE/ACPNBB=(ZTNSA1(ROP1+ZTNSA0+ZTNSA2)

((FDUACT·FRDP1)+FLDCOMPL·FRPK·ZLNADJ7·ZLNADJ8·ZLANDJ9))+(ZTNSB1(ROP1+ZTNSB0+ZTNSB2))·(FRDP1.multidot.FLDCOMPL))

An ATMP adder 730-30 calculates the number of zeros to the right of theleast significant digit of the operand with the larger scale factor. TheZASFB switch 730-28 selects the adjusted scale factor binary signals ASF0-9 which are added to the quantity 63 if the operand 2 scale factor islarger or subtracted from the quantity 63 if the operand 1 scale factoris larger. The output signals ATMP 3-9 are loaded into an RTMP register730-100. Bit positions RTMP 0-3 store a binary count of the number ofwords of the operand to the left of the word containing the leastsignificant digit position. Bit positions RTMP 4-6 store a binary numberindicating the least significant bit position. Signals RTMP 4-6 indicatethe number of zeros to the right of the least significant digit.

A comparator 730-104 compares signals RTMP 0-3 and RLMP 0-3. Thedifference equals the number of words of the operand to be received bythe decimal unit 730 from cache 750. The binary word count RLMP 0-3 isincremented each time a word of the operand is loaded into the RDODregister 730-154. The difference between binary signals RTMP 0-3 andRLMP 0-3 is zero when the last word of the operand is received in thedecimal unit 730 thereby enabling the A=B output signal of thecomparator 730-104. This enables the TMSC 0-3 output of TMSC logiccontrol 730-106 which is a binary count of the number of zeros to theright of the least significant digit. This count is applied to the TMSClogic control 730-106 by signals RTMP 4-6. The TMSC 0-3 count is appliedto a ZIDML shifter 730-120. The number of low order digit positions tothe right of the least significant digit to be forced to ZERO isindicated by the number of successive signals starting with the ZIDML 7signal which are forced to ZERO. The ZIDML 0-7 signals are applied tothe [EZID 0-7 logic control 730-132. The output signals [EZID 0-7reflect the ZMIDL 0-7 signal states and enable the high order positionsof the ZID switch 730-150, forcing the low order positions to the rightof the least significant digit to ZERO.

The ASFA 33-36 signals are received from the address preparation unit704-3 for operands 1, 2 and 3 and are stored in registers RCP0, RCP1 andRCP2 respectively of a register bank 730-42.

The ASFA 33 signal indicates the least significant bit of the cache 750address of the high order word of the operand indicating whether thisword is from an odd or even memory address location. This is used in thecompacting of operands having 9-bit characters which are received in thedecimal unit 730 as 4 decimal characters per word to 8-decimal digitsper word, which is sent to the execution unit 714.

For 9-bit character operands, signals ASFA 34 and 35 indicate theposition of the leading character in the high order word of the operand.For 4-bit character operand words, signals ASFA 34-36 indicate theposition of the leading character in the high order word of the operand.

The operand pointer stored in register RCP0 is selected through the RCP0position of a ZCPA switch 730-44 and applied to a ZCPNB switch 730-48.The ZCPA 0-2 position of the ZCPNB switch 730-48 is selected if operand1 comprises 9-bit characters and the ZCPA 1-3 position is selected ifoperand 1 comprises 4-bit characters. Signal [ONE/ACPNBB is applied toan input of the ACPNB adder 730-50 and is added to the ZCPNB 0-2 withalsif operand 1 has a leading sign. This is indicated by the 1-bit of theRTNS0 register being a ZERO. The ACPNB 1-3 output of the adder points tothe most significant decimal digit position of the high order word ofoperand 1 as it is received in the decimal unit 730 from cache 750.

An ACPDF adder 730-52 subtracts the high order digit position from theACPR 7-9 signal output of the ACPR adder 730-62. The ACPR 7-9 binarysignal indicates the number of ZEROs to the left of the most significantdigit in the operand high order word to be transferred to the executionunit 714. Subtracting binary signals ACPNB 1-3 from ACPR 7-9 in theACPDF adder 730-52 gives an output binary value signal ACPDF 0-3 whichis the amount the operand being received from cache 750 is shifted to beproperly aligned for transfer to the execution unit 714. This shiftvalue is stored in an RDSC register 730-58 through a switch 730-56. Theoutput of the RDSC register 730-58 is applied to a shifter 730-156through a ZDSC switch 730-72. The ACPDF adder 730-52 calculation is madeseparately for operand 1 and operand 2 and aligns the operands relativeto each other for numeric processing in the execution unit 714.

A ZCPWC switch 730-46 selects the operand character pointer for 4-bitand 9-bit character operands and applies it to an ACPWC adder 730-66where a quantity ONE is subtracted to give an output signal ACPWC 0-3. AZLNT switch 730-64 selects the operand 1 length for the operand 1 loadand the operand 2 length for the operand 2 load for input to an ASWCadder 730-68 where it is added to the ACPWC 0-3 binary signal. A ZSWCswitch 730-70 selects an ASWC 0-4 switch position for a 9-bit characteroperand and an ASWC 0-3 switch position for a 4-bit character operandand applies the ZSWC 0-4 binary output for storage in an RSWC register730-110.

The RSWC register 730-110 stores a binary count of the number of wordsin the operand to be transferred from cache 750 to the decimal unit 730.The count in the RSWC register 730-110 is decremented by a [CNTDWN-RSWCsignal each time a word is received in the RDID register 730-158. Theboolean expression for the signal is

[CNTDWN-RSWC=([LDRRWC(FDID·(FOP1LD+FOP2LD)·DFCO+[$RDODA.multidot.(DUCMD303+FOPSTR)))

[LDRRWC=(FDUACT·FRDP1+SFOP2LD+FLDCOMPL·(FOPSTR+DUCMD 303))

DFCO=RSWC0·RSWC1·RSWC2·RSWC3·RSWC4

[$RDODA=(FDATA-AV+DUCMD 203+DUCMD 310+DUCMD 309+FRPK·DUCMD303+FRPK·FALT·FSWRT)·DUCMD 311

The RSWC register 170-110 at zero indicates that all the words of theoperand have been received by the decimal unit and the DFCO signaloutput sets the FDFD flag in status flag control logic 730-202.

The ARWC adder 730-60 output signals ARWC 0-6 are stored in an RRWCregister 730-88 when the [LDRRWC signal is at logical ONE. The RRWCregister 730-110 stores the number of words in the operand to betransferred to the execution unit 714 during the load operation. Eachtime a word of an operand is loaded into the RDOD register 730-154, theRRWC register 730-110 is decremented by one when the [CUTDWN-RRWC signalis at logical ONE. The boolean expression is

[CNTDWN-RRWC=(DTECO·(FOP1LD+FOP2LD)·[$RDODA+((FOPSTR+DUCMD303·(DMSDRGTE+(DMSEQ·RDSC0)))·FALT·(FSWRT·DMSDRGTE+(ZTNSA0·FCPCO+ZTNSA0)·FSWRT)).multidot.FRPK+FRPK·DUCMD303·(ZTNSA0·FCPC0+ZTNSA0))

DTECO=RRWC0·RRWC1·RRWC2·RRWC3·RRWC4.multidot.RRWC5·RRWC6

The RRWC register 730-110 at ZERO indicates that all the decimal digitsof the operand have been sent to the execution unit 714 by the DTECOoutput signal setting the FDTED flag in status flag control logic730-202.

The FOP1LD flag is set by the firmware initiating a DUCMD 301 signalindicating a "Read Operand through Decimal Unit" operation. The FOP1LDflag is reset when the DFCO and DTECO output signals indicate that boththe RSWC register 730-110 and the RRWC register 730-88 respectively havedecremented to ZERO during the operand 1 load operation. The FRDP1 flagset indicates that the DUCMD 301 has been issued to read operand 1through the decimal unit 730.

The FOP2LD flag is set by the firmware to read operand 2 when the DUCMD301 has been issued with the FRDP1 flag set. The FOP2LD flag is resetand the FLDCOMP flag is set indicating that the load operation iscomplete when both the RRWC and RSWC registers have decremented to ZEROduring the operand 2 operation, i.e., both operands 1 and 2 have beenprocessed in the decimal unit 730 and transferred to the execution unit714.

An RLZC1 register 730-96 and an RLZC2 register 730-98 are used toindicate to the firmware the number of zeros to the left of the mostsignificant non-zero digit in operand 1 and operand 2 respectively.Register positions RLZC1 1-3 and RLZC2 1-3 are loaded with the ARWC 4-6output signals of the ARWC counter 730-60. This essentially prebiasesthe word count portion of the RLZC1 and RLZC2 registers, bit positionsRLZC1 and RLZC2 0-3 with the value of 7 words minus the number of wordsto be sent to the execution unit (binary value of the ARWC counter730-60 bit positions ARWC 4-6) and equals the number of words not beingsent to the execution unit 714. The number of leading zeros to the leftof each operand is sensed at the output of the ZID 730-150. The ZID04-35 signals are applied to the load zero count logic 730-182 and theoutput LZC 0-3 indicates the number of leading zeros in the word. SignalLZC0 being a ONE indicates that all the decimal digits of the word arezero, a ONE is added to the RLZC1 or RLZC2 registers at the bit 3position and the next word is received from cache 750. Again, if theword contains all zeros then signal LCZ0 is a ONE, a ONE is again addedto the bit 3 position and the next word is received from cache 750.Assume that the next word received from cache 750 does not contain allzeros, then the signals LZC 1-3 indicate the number of zeros to the leftof the first non-zero decimal digit. This sets an FZCF flag indicatingto the logic that the ZERO to the left count is completed for thisoperand. This count is transferred through a ZEDC switch 730-82 to theRLZC1 and RLZC2 registers and stored in bit positions RLZC1 4-6 andRLZC2 4-6 for their respective operands.

The binary values stored in the RLZC1 register 730-96 and RLZC2 register730-98 are the count of the number of decimal digit positions to theleft of operands 1 and 2 respectively to fill the 64 decimal digitpositions set aside in the execution unit 714 for each operand.

The output of the RLZC1 and RLZC2 registers are transferred underfirmware control through a ZLZC switch 730-76 position 3 of the ZIDswitch 730-150, through the ZDOD switch 730-152 to the RDOD register730-154. The ARWC signal input to the ZLZC switch 730-76 provides thenumber of words transferred for a long operand. The ATMP signal inputprovides the word location to which the rounding constant is added. Theboolean expressions controlling the RCZC1 register 730-96 and the RCZC2register 730-98 for loading the low order positions of the registers are

[$RLZC1L=([$RDODA·FOP1LD·FZCF+(DUCMD 305+FCZ0)·DEDCZ)

[$RLZC2L=([$RDODA·FOP2LD·FZCF+(DUCMD 305+FCZ0)·DEDCZ)

The boolean expressions for loading the high order positions of theregisters are:

[LDRLZC1U=SFOP1LD+(DUCMD 305+FCZO)·DEDCZ

[LDRLZC2U=SFOP2LD+(DUCMD 305+FCZO)·DEDCZ

DEDCZ=EDC0·EDC1·EDC2·EDC3

The registers are incremented by

[CNTUPRLZC1U=[$RDODA·FOP1LD·FZCF·LZCO

[CNTUPRLZC2U=[$RDODA·FOP2LD·FZCF·LZCO

SFOP1LD=(DUCMD 301·FRDP1·FPOA·(D1EQOVP·D2EQOVP.multidot.LONG+FCRP1))

SFOP2LD=(FOP1LD·FMVN·(DUCMD301+FRDP2)(DFCO·FDID·DTECO·[$RDODA+DFCO.multidot.FDID·FDTED+DTECO·[$RDODA·FDFD)+FOP1LD.multidot.FMVN·DUCMD301·FRDP1)FPOA)

D1EQOVP=(DBITX·ROP1·ZTNSAO)

D2EQOVP=(DBITZ·ROP1·ZTNSBO)

LONG=ALNDAGTE16+ALNDBGTE16+ALNSGTE16·FMYDV+D1EQFLP+D2EQFLP

ALNDAGTE16=ALNDA1+ALNDA2

ALNDBGTE16=ALNDB1+ALNDB2

ALNSGTE16=ALNS3+ALNS4+ALNS5

Decimal Unit--Load Operation

Operands are transferred from cache 750 to the decimal unit 730 oversignal bus ZDI 0-35 and are loaded into an RDID register 730-158 underfirmware control. The firmware initiates a DUCMD 301 "Read OperandThrough Decimal Unit" command. This sets the FRDP1 and the FOP1LD flagsto condition the decimal unit 730 logic to receive operand 1 from cache750.

The RSWC register 730-110 is loaded with the number of words to bereceived from cache 750. The RRWC register 730-88 is loaded with thenumber of words to be sent to the execution unit 714. The RSWC register730-110 is decremented by ONE for each word received from cache 750. TheRRWC register 730-88 is decremented by ONE for each word sent to theexecution unit 714. The boolean expressions for the loading anddecrementing the RSWC and RRWC registers 730-110 and 730-88 respectivelyare:

[LDRSWC=((FDUACT·FRDP1)+(FLDCOMPL·DUCMD 303·FOPSTR)+SFOP2LD)

[CNTDWN-RSWC=([LDRRWC(FDID(FOP1LD+FOP2LD)·DFCO+[$RDODA·(DUCMD303+FOPSTR)))

[LDRRWC=(FDUACT·FRDP1+SFOP2LD+FLDCOMPL(FOPSTR+DUCMD 303))

[CNTDWN-RRWC=(DTECO·(FOP1LD+FOP2LD)·[$RDODA+((FOPSTR+(DUCMD303(DMSDRGTE+(DMSEQ·RDSCO))))·FALT·(FSWRT.multidot.DMSDRGTE+(ZTNSAO·FCPCO+ZTNSAO)·FSWRT))·FRPK+FRPK·DUCMD303·(ZTNSAO·FCPCO+ZNTSAO))

The FOP1LD flag is reset on the cycle following the RSWC and RRWCregisters counting down to zero by the DFCO and DTECO outputs at logicalONE. The boolean equations are listed supra. This indicates that all ofthe operand 1 words have been received by the decimal unit 730 and sentto the execution unit 714. The firmware initiates another DUCMD 301command which sets the FOP2LD flag since the FRDP1 flag is still setconditioning the decimal unit 730 to receive operand 2 words. Again theRSWC register 730-110 and the RRWC register 730-88 are loaded withnumber of words received from cache 750 and sent to the execution unit714 respectively and counted down to zero indicating to the decimal unit730 that operand 2 was received, processed, and transferred to theexecution unit 714. The FOP2LD flop is then reset.

The operand may contain 4-bit or 9-bit decimal digits. Operandscontaining 4-bit decimal digits are processed through the decimal unit730 differently from operands containing 9-bit decimal digits. Assumingthat the operands contain words with 4-bit decimal digits and the firstword is stored in the RDID register 730-158. Control signal [1ZPK isforced to a ONE selecting the 1 position of a ZPK switch 730-160. TheRDID 0-35 output signal is compacted from a 36 bit word to a 32 bit wordin the selected position 1 of the ZPK 730-160 switch and outputs assignal bus ZPK 0-31 which may indicate up to eight 4-bit decimal digits.The negated output signal bus ZPK 0-31 is stored in an RPK register730-162. The decimal digits of this data word are the high order digitsof the operand. If the decimal digits of the first word of the operandoutputting the ZPK switch 730-160 have a sufficient number of decimaldigits to be sent to the execution unit 714 as specified by the decimalunit 730 logic then the necessary switches are conditioned by theirrespective control signals to load the RDOD register 730-154. In thiscase the ZPK 0-31 output signals are selected through a ZPKR switch730-164. The output signals ZPKR 0-31 are applied to the shifter 730-156where they are shifted to the right an amount specified by the ZDSC 1-3binary shift count output of the RDSC register 730-58. The ZDS 0-31output signals are applied to a ZID switch 730-150 where non decimaldigit characters such as signs and exponents and also non-operandreplacement characters are replaced by zero under control of the [EZID0-3 ZID switch enable signal output of the [EZID control logic 730-132.The output signals ZID 4-35 are selected by position 0 of the ZDODswitch 730-152. ZDOD 4-35 output signals are stored in the RDOD register730-154.

If the data word made up of 4-bit digits will not fill a sufficientportion of the RDOD register 730-154 for transfer to the execution unit714, then the first word remains stored in the RPK register 730-162 andthe next data word of 4-bit digits is transferred from cache 750 to theRDID register 730-158 under firmware control. The second data word isapplied to the shifter 730-156 through the ZPK switch 730-160 and theZPKR switch 730-164. The first data word stored in the RPK register730-162 is applied to the shifter 730-156 through a ZPKL switch 730-166.The shift count signal ZDSC 1-3 selects 32 of the 60 inputs to theshifter 730-156. The ZDS 0-31 output signals are stored in the RDODregister 730-154 through the ZID switch 730-150 and the ZDOD switch730-152. Necessary zeros to the left and right are added to the ZDS 0-31shifter output under control of the [EZID 0-7 enable signals while theoperand word is switched through the ZID switch 730-150.

If the operand from cache 750 to the decimal unit 730 consists of a9-bit decimal digit the first data word containing a maximum of 4decimal digits is stored in the RDID register 730-158. The 9-bit decimaldigits are stripped of the 5 high order bits of each decimal digit andcompacted as the word is switched through the selected 2 position of theZPK switch 730-160 and are stored in either the left 16-bits of the RPK0-15 register 730-162 if from an even address in cache 750 or are storedin the right 16-bits of the RPK 16-31 register 730-162 if from an oddaddress in cache 750.

If a data word may be made up to send to the execution unit 714 then itinputs the shifter 730-156 through the ZPK switch 730-160 and the ZPKRswitch 730-164. Note that the decimal digits are repeated in ZPK 0-15and ZPK 16-31 switch position 2 as the digits pass through the ZPK 0-31switch. The extraneous digits, the sign, exponent and rewrite digits arestripped from the data word in the ZID 730-150 switch. The ZDS 0-31output of the shifter 730-156 is stored in the RDOD register 730-165through positions 0 of the ZID switch 730-150 and the ZDOD switch730-150 and the ZDOD switch 730-152.

Assuming that the first data word comprising 9-bit characters wasreceived from an even cache 750 address and stored in RPK 0-15 register730-162, the second data word would be received from an odd cache 750address and would be stored in the RPK 16-31 register 730-162.

The second data word is applied to the shifter 730-156 through the ZPKswitch 730-160 and the ZPKR switch 730-164 after being stripped of thehigh order 5-bits of each 9-bit decimal digit and packed into bothhalves of the ZPK 0-31 data word. The first data word stored in eitherthe odd address or even address half of the RPK register 730-162 isapplied to the shifter 730-156 through the ZPKL switch 730-166.

Control signals [1ZPK and [2ZPK select one of four positions of the ZPKswitch 730-160. Position 0 is selected for the store operation, position1 for the 4-bit digit operand, position 2 for the 9-bit digit operandand position 3 for the rounding operations. The boolean equations are

[1ZPK=ZTNSAO·FOP1LD+ZTNSBO·FOP2LD+DUCMD 309

[2ZPK=ZTNSAO·FOP1LD+ZTNSBO·FOP2LD+DUCMD 309

Control signal [$RPKU enables the loading of the RPK register 730-162,positions RPK 0-15 for 9-bit operands from an even cache 750 address,and 4-bit operands. Control signal [$RPKL enables the loading of RPKregister 730-162, positions RPK 16-31 for 9-bit operands from an oddcache 750 address, and 4-bit operands.

The boolean equations are

[$RPKU=DUCMD305+FDID·(ZTNSAO·FOP1LD+ZTNSBO·FOP2LD+ZTNSAO.multidot.FOP1LD·FCPCO+ZTNSBO·FOP2LD·FCPCO)+FRPK.multidot.FOPSTR·(FALT·FSWRT+FALT·FSWRT·FSND))

[$RPKL=DUCMD305+FDID·(ZTNSAO·FOP1LD+ZTNSBO·FOP2LD+ZTNSAO.multidot.FOP1LD·FCPCO+ZTNSBO·FOP2LD·FCPCO)+FRPK.multidot.FOPSTR·(FALT·FSWRT+FALT·FSWRT·FSND))

Control signals [0ZPKL and [0ZPKR enable respectively the ZPKL switch730-166 and the ZPKR switch 730-164. Control signal [1ZPKL, at logicalONE selects the ZPK 4-31 bit positions from ZPKL switch 730-166 and theRPK 16-31 bit position from ZPKR switch 730-164. Control signal [1ZPKRU,at logical ONE, selects the RPK 0-15 bit positions of the ZPKR switch730-164.

[0ZPKA=FOP1LD+FOP2LD+(FOPSTR+DUCMD303)·(FRPK·(DMSDREQ10·RDSCO+DMSDREQOM1.multidot.RDSCO)+FRPKFMSDRN·(DMSDRLTM1+FMSDRGTE DMSDRLTM2)·FMSEQ))

[0ZPKR=FOP1LD+FOP2LD+(FOPSTR+DUCMD303)·(FRPK·(DMSDREQ21·RDSCO+DMSDREQ10·RDSCO)+FRPK·FMSDRN·(FMSDRGTE·DMSDRLTM1+RRWCO).multidot.DMSEQ)+DUCMD309·FRPK+D1EQFLP+(ATMP 0-6)·FRCMD+(ATMP 0·1·2·3·4·5·6).multidot.FRCMD))

[1ZPKL=(DMSDRQEQ1·RDSCO+DTECO·RDSCO)·FRPK.multidot.(FOPSTR+DUCMD 303)

[1ZPKRU=(FOP1LD·ZTNSAO+FOP2LD·ZTNSBO)·RDSC1+(FOPSTR+DUMCD303)·FRPK·(DMSDRWEQ1·RDSCO+DTECO·RDSCO

DMSDREQ10=DTEC0+DMSDRWEQ1

DMSDRWEQM1=RRWC0·FFWC1·RRWC2·RRWC3·RRWC4·RRWC5·RRWC6

DMSDREQOM1=DTEC0+DMSDRWEQM2

DMSDRLTM1=RRWC0·DMSDRWEQM1

DMSDRLTM2=RRWCO·(RRWC1·RRWC2·RRWC3·RRWC4·RRWC5)

DMSDREQ21=DMSDRWEQ2+DMSDRWEQ1

DTECO=RRWCO·RRWC1·RRWC2·RRWC3·RRWC4.multidot.RRWC5·RRWC6

DMSDRWEQ1=RRWC0·RRWC1·RRWC2·RRWC3·RRWC4·RRWC5·RRWC6

DMSDRWEQ2=RRWC0·RRWC1·RRWC2·RRWC3·RRWC4·RRWC5·RRWC6

The boolean expressions for the control signals that condition theoperand words during both the load and store operation are as follows

[1ZlD=DUCMD 203+DUCMD 310+DUCMD 311+FRPK·FRCMD·DUCMD 309

[2ZlD 0-7=DUCMD 310+DUCMD 311+(FRPK·FRCMD·DUCMD 309)+ZCRDG-MASK

[1ZDOD0=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR0+[2ZSMR0)

[1ZDOD1=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR2+[2ZSMR2)

[1ZDOD2=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR4+[2ZSMR4)

[1ZDOD3=([STRPKD+[UNPKDLWR+[UNPKDUPR ([1ZSMR6+[2ZSMR6)

[2ZDOD0=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR0+[2ZSMR0))

[2ZDOD1=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR2+[2ZSMR2))

[2ZDOD2=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR4+[2ZSMR4))

[2ZDOD3=(4STRPKD+[UNPKDUPR+[UNPKDLWR ([1ZSMR6+[2ZSMR6)

[1ZSMR 0-7=SIGNMASK+REWUM 0-7+REWLM 0-7

[2ZSMR 0-7=EXPMASK+REWUM 0-7+REWLM 0-7

[STRPKD=(ZTNSA0 (DUCMD 303+FOPSTR)

[UNPKDLWR=(ZTNSA0 (DUCMD 303+FOPSTR)·FCPC0)

[UNPKDUPR=(ZTNSA0 (DUCMD 303+FOPSTR)·FCPC0

An ACPR adder 730-62 calculates the number of zeros digits to the leftof the operand necessary to fill a 64 digit block of storage. Theadjusted length ZLNADJ 0-9 output of switch 730-26 is subtracted from64, the maximum number of digits that will be transferred between thedecimal unit 730 and the execution unit 714. The output of the ACPRadder 730-62 is stored in the RLMP register 730-102. The RLMP 4-6 outputsignals, the low order 3-bits, store the number of 4-bit decimal digitpositions to the left in the high order word to be forced to zero and isapplied to the shift count input of a ZIDMU shifter 730-130. Thoseoutput signals ZIDMU 0-7, which indicate zero digits to the left, areforced to ZERO. This forces the indicated outputs of [EZID logic control730-132, signals [EZID 0-7 to ZERO thereby forcing the selected digitpositions of the ZID switch 730-150 to ZERO of the first word of theoperand received by the decimal unit 730. If the operand had a leadingsign, it would have been replaced by ZERO in the ZID 730-150 switchsince the sign character position count was subtracted from each operandlength in adders ALNDA 730-18 and ALNDB 730-20 respectively. Also,rewrite characters in the operand word would be replaced by ZERO's.

An ATMP adder 730-30 calculates the number of zeros to the right of theleast significant digit position of the operand having the larger scalefactor. Switch ZASFB 730-28 selects the number of zeros to the right foroperand 1 or operand 2 during that cycle in which the operand transfersfrom cache 750 to the decimal unit 730.

If the operand 1 scale factor is larger than the operand 2 scale factorthen the ASF 0-9 input to switch ZASFB 730-28 is a positive number whichis subtracted from 63 in the ATMP adder 730-30 and the difference,output signals ATMP 3-9, are stored in an RTMP register 730-100. The loworder positions RTMP 4-6 input a TMSC logic control 730-106 and outputas signals TMSC 0-3 which are applied to the shift count input of aZIDML shifter 730-128. This forces the ZIDML 0-7 output signals toindicate the number of digit zeros to the right of the operands. TheZIDML 0-7 output signals are applied to the [EZID logic control 730-132.The [EZID 0-7 output signals condition the indicated low order digitpositions of the ZID switch 730-150 to ZERO thereby stripping trailingsign, exponent, and rewrite characters from the operand word.

Signals RTMP 0-3 the output of register 730-100 and signals RLMP 0-3 theoutput of register 730-102 indicate the cycle on which the operand wordwhich requires the ZEROs to the right is transferred from the decimalunit 730 to the execution unit 714. The 64 decimal digit maximumtransfer is made up of eight words of 8-decimal digits per word. SignalsRLMP 0-3 are a binary representation of the number of words to the leftof the word containing the most significant digit that contains allzeros. Signals RTMP 0-3 are a binary representation of the number ofwords in the maximum transfer minus the word in which ZEROs to the rightare forced. Plus 1 is added to binary signals RLMP 0-3 each timeregister RDOD 730-154 is loaded. Signals RTMP 0-3 and RLMP 0-3 arecompared in a comparator 730-104. Signals TMSC 1-3 are forced to ZERO onthe cycles where binary signals RTMP 0-3 is greater than binary signalsRLMP 0-3 ZEROs to the right are forced in the ZID switch 730-150 on thetransfer cycle where comparator 730-104 indicates that the binary valuesof RLMP 0-3 and RTMP 0-3 are equal.

Control signal [$RTMP enables the input loading of RTMP register730-100, and the RLMP 4-6 bit positions of the RLMP register 730-102.Control signal [$RTMP enables the output of the RLMP 0-3 bit positionsof the RLMP register 730-102.

Control signal [ZERO/RLMPL enables the output of the RLMP 4-6 bitpositions. Control signal [CNTUP-RLMPU increments the RLMP 0-3 bitpositions. The boolean equations are

[$RTMP=(FDUACT·FRDP1+SFOP2LD)

[ZERO/RLMPL=(FFDO+(FOP1LD+FOP2LD)·[2ZIDA))

[CNTUP-RLMPU=((FOP1LD+FOP2LD)·[$RDODA·SFOP2LD)

Decimal Unit--FIG. 3--Store Operation

The FPOP3 cycle loads descriptor 3 information into register RSIR704-154 for a 3 descriptor instruction. In decimal arithmeticinstructions, descriptor 3 defines the field into which the results ofthe calculation of the descriptor 1 and descriptor 2 operands arestored. Some instructions store the result of the descriptor 1 anddescriptor 2 operand calculations in the field defined by descriptor 2.In either case the RSIR register 704-154 stores the descriptorinformation and transfers it to the decimal unit 730 for the storeoperand 3 operation. The decimal unit 730 receives operand 3 from thecharacter unit 720 over the RCHU 0-35 signal bus. The decimal unitunpacks it, adds the sign and exponent if required, positions theoperand 3 digits within the word, places the proper number of zeros tothe left and right of the operand, adds required ASCII or EBCDIC zonebits and reinstates the portion of the first and last words of theoperand that are not defined as part of the operand. The decimal unit730 sets up the necessary controls in the logic to receive operand 3,manipulate it and store it in cache 750 in conformance with itsdescriptor information.

The operand 3 scale factor signals RSIR 24-29 inputs switch ZSFN 730-2and are stored in register RSF2 of register bank 730-4. For the casewhere the input operands were such that the decimal unit 730 did thescale factor alignments, the ZSFA switch 730-6 selects the contents ofthe RSF2 register, and the ZSFB switch selects the contents of eitherthe RSF0 or RSF1 register of register bank 730-4. The register selectedis the one storing the smaller scale factor of operand 1 or 2. The FSSFDflag which is set by the scale factor comparison during the loadoperation makes the selection.

Control signals 4WRRSF1 and 4WRRSF2 select 1 of the RSF 0-4 registers730-4 in which the scale factor is stored. The boolean expressions are

[WRRSF1=((F3DESC+FMVN) FLDCOMPL·FPOP·D1EQFLP) (DUCMD305·FCZ0)+RDESC1·FPOP+(FMYDV+FPTL+FPFL) DUCMD 308·D1EQFLP(FMVN+F3DESC)·FPOP·FLDCOMPL

[WRRSF2=((FMYDV+FPTL+FPFL) DUCMD 308·FPOP·FLDCOMPL·D1EQFLP (FMVN+F3DESC)+RDESCO·FPOP+(F3DESC+FMVN) FLDCOMPL·FPOP·D1EQFLP)

The ZSFB switch 730-8 output is subtracted from the ZSFA switch 730-6output in the ASF adder 730-10. The ASFO-9 output signal inputs the ALNSadder 730-24 and is also stored in the RSCLM register 730-144 where itserves as a pointer to the least significant end of the data to beactually stored.

For a floating point store operation, the RSF3 register of register bank730-4 stores the adjusted length output of the ALNDA adder 730-18 andthe RSF2 register holds the effective digit counts of the internalresults the first time the count is taken, i.e., the output of the AEDCadder 730-86 and the ZEDCl-3 output of the ZEDC switch 730-82 inputtingthe ZSFN switch 730-2. In this case the contents of the RSF3 register isselected through the ZSFA switch 730-6 and the contents of the RSF2register is selected through the ZSFB switch 730-8 and are subtractedfrom each other in the ASF adder 730-10. Again the ASFO-9 output isapplied to the input of the ALNS adder 730-24 and the RSCLM register730-144. However, for the purposes of obtaining the zero or effectivedigit count, the first time the operand is examined, the contents of theRSCLM register 730-144 are over written in forming up the inputs to theoutput zero and overflow detection logic 730-80. After the first count,if the number of effective digits is greater than the adjusted length ofoperand 3, the decimal overflow flag FDOFL will be set and thecalculation of the effective digit count from RSF2 register contentsminus the adjusted length from the contents of the RSF3 register will beenabled at the output of the RSCLM register 730-144 for a subsequentzero and overflow examination.

The length field signals RSIR 30-35 are stored in register RLND2 ofregister bank 730-12 and are switched through the RLND2 position of theZLNDA switch 730-16 to input the ALNDA adder 730-18.

Control signals [1ZSFA and [2ZSFA select the outputs of the RSF 0-3registers 730-4 for application to the plus input of ASF adder 730-10.Control signals [1ZSFB and [2ZSFB select the RSF 0-3 outputs forapplication to the minus input of ASF adder 730-10.

The boolean expressions are

[1ZSFA=F3DESC·FLDCOMPL·(FMVN·D1EQFLP)

[2ZSFA=F3DESC·FLDCOMPL+FMVN·FLDCOMPL·F1EQFLP

[1ZSFB=FMVN·FLDCOMPL+FMVN·FSSFD·FLDCOMPL.multidot.(F3DESC+FMVN)·D1EQFLP·(FMYDV+FPTL+FPFL)+FLDCOMPL.multidot.(F3DESC+FMVN)·D1EQFLP+FLDCOMPL·(F3DESC+FMVN)·D1EQFLP·(FMYDV+FPTL+FPFL)+FLDCOMPL·(F3DESC+FMVN)

[2ZSFB=FLDCOMPL·(F3DESC+FMVN)·D1EQFLP+FLDCOMPL·(F3DESC+FMVN)·D1EQFLP·(FMYDV+FPTL+FPFL)

The sign and decimal type signals RSIR 21-23 are stored in registerRTNS2 of register bank 730-32 and are transferred through the RTNS2switch position of the ZTNSA switch 730-36 to the decode logic 730-38where the correction factors to the length are determined. If operand 3is a nine-bit floating point number then 2 digits are subtracted fromthe length. If operand 3 is scaled with a leading or trailing sign then1 digit is subtracted from the length. A four-bit floating point numberwill have 3 digits subtracted from the length. The boolean expressionsfor signals DBITX and D1EQFLP which are applied to the ALNDA adder730-18 and the ALNDB adder 730-20 were described supra.

The output of decode logic 730-38 is applied to the other inputs of theALNDA adder 730-18 and subtracts from signals ZLNDA 0-5. The output ofthe ALNDA adder, signals ALNDA 0-6, adjusts the length to indicate thenumber of decimal digits in operand 3. The ALNDA 0-6 output signals areapplied through the ZALND switch 730-22 to the input of the ALNS adder730-24. The scale factor signals ASF 0-9 are added to the ALNDA lengthand the output signals ALNS 0-9 is the adjusted length of operand 3. Theoutput ALNS 0-9 is applied through the zero position of the ZLNADJswitch 730-24 to input adders ARWC 730-60 and ACPR 730-62 and is storedin an RSCUM register 730-78. Adder ACPR subtracts the adjusted lengthZLNADJ 3-9 from 64 and its output signals ACPR 3-9 indicates theposition of the most significant digit to be stored within the internalresult field. Signals ACPR 7-9 indicate the position of the mostsignificant digit within the word of the operand containing the mostsignificant decimal digit. The signals ACPR 7-9 are applied to the inputof the ACPSC adder 730-54.

The output of the ARWC adder 730-76, signals ARWC 0-6 are applied to theRRWC register 730-88 and indicates the location of the operand wordcontaining the most significant digit to be transferred from the decimalunit 730 to cache 750. A ONE is added to the ARWC adder in the case ofoperand 3 having a leading sign which would result in another word beingtransferred to cache 750.

For the floating point operation during the first examination for zeroor overflow, i.e., the DUCMD 304 check zero overflow command and for anysubsequent examinations for which the overflow flag FDOFL has not beenset then the ALNDA adder 730-18 output is selected through the ZINADJswitch 730-26. If on a floating point output result the decimal overflowflag FDOFL had been set then the ALNS adder 730-24 output is selectedthrough the ZLNADJ switch 730-26. The ALNS adder 731-24 forms thedifference between the adjusted length output of the ALNDA adder 730-18and the effective digit count minus the adjusted length from the ASFadder 730-10 output.

The starting character pointer signals ASFA 33-36 are stored in registerRCP2 of register bank 730-42 and are selected by the RCP2 switchposition of the ZCPA switch 730-44. Signal ZCPA 0-3 inputs the ZCPNBswitch 730-48. If operand 3 is made up of 4-bit characters then signalsZCPA 1-3 are selected and if operand 3 is made up of 9-bit charactersthen signals ZCPA 0-2 are selected as the output signals ZCPNB 0-2 toinput the ACPNB adder 730-50. A ONE is added to the ACPNB adder if theoperand has a leading sign. The output signals ACPNB 0-3 are applied tothe input of an ACPSC adder 730-54. Switch 730-56 by means of theFLDCOMPL status flag selects signals ACPSC 0-3 for storage in registerRDSC 730-58. The ACPSC adder 730-54 subtracts the most significant digitposition within the internal operand word as indicated by the ACPR 7-9signals from the digit position within the in storage word of the mostsignificant digit as indicated by the ACPNB signal to give the value ofthe number of digit positions the operand to be stored is shifted. Thisvalue represented by signals ACPSC 0-3 stored in register RDSC 730-58 isthe shift count for the ZDS shifter 730-156.

The ASWC adder 730-68 output signals ASWC 0-6 provides input signals toZSWC switch 730-70, ZRLMP switch 730-112, ZSMP switch 730-116 and theZEMP switch 730-120. The outputs of the switches are applied to shifters730-114, 730-118 and 730-122. The shifter outputs are applied to control[1ZSMR logic 730-142 and control [2ZSMR logic 730-146 for generating the[1ZSMR 0-7 and [2ZSMR 0-7 signals. These signals are applied to the ZSMRswitch 730-180 for loading the sign, exponent and rewrite charactersinto the operand 3 words. The starting character pointer signals ZCPA0-3 are applied to the input of switch 730-46 whose output, signalsZCPWC 0-2 are derived from signals ZCPA 1-2 for a 9-bit characteroperand and signals ZCPA 1-3 for a 4-bit character operand. SignalsZCPWC 0-3 are applied to the input of adder ACPWC 730-66. The decimaldigit ONE is subtracted and the output, signals ACPWC 0-3 are applied tothe input the ASWC adder 730-68. The length field of operand 3, signalsZLNDA 0-5, are added to the starting character pointer minus ONE toindicate the character pointer for the last decimal character in theoperand.

The first word of operand 3 is received from the character unit 720 oversignal lines RCHU 4-35, through buffer 730-168 which generates theassertion signals RCHU 4-35 and the negation signals RCHU 4-35.

Control signals [1ZPK and [2ZPK select the zero position of the ZPKswitch 730-160 and RCHU 4-35 appear at the output of the switch assignals ZPK 0-31 and ZPK 0-31.

For the long operand, that is operands greater than 15 decimal digitsthe operand is transferred from the RCHU register 720-10 a word at atime with the word containing the most significant decimal digits beingtransferred to the decimal unit 730 first.

If a sign is required for the operand, the firmware loads the RSGNregister 720-134 over the ZADSP 3-11 signal lines from the auxilliaryarithmetic and control unit 722 in response to a DUCMD 307 command "Loadthe DU Sign Register". The output of the RSGN register 730-14 is appliedto selected position 1 of the ZSMR switch 730-180. The characterlocation in ZSMR switch position 1 is selected as follows. The output ofthe ASWC adder 730-68 points to the low order character position of atrailing sign. The output of the ZCPA switch 730-44 points to theleading sign character position. A ZSMP switch 730-116 selects atrailing or leading sign for 4-bit or 9-bit operands. The ZSMP 1-3 shiftcount is applied to an SIGNM shifter 730-118. The logical ZERO input tothe SIGNM shifter 730-118 selects the one of the SIGNM 0-7 outputsignals for 4-bit operands. The logical ZERO and the ZTNSA0 signalsselect two adjacent signals of the SIGNM 0-7 output signals for 9-bitoperands. The signal SIGNM 0-7 output of the shifter selects the [1ZSMR0-7 output signal of control [1ZSMR 730-142 which selects 1 of 8 of theswitch 1 positions of the ZSMR switch 730-180 for the 4-bit decimaldigit operand sign or 2 adjacent positions for the 9-bit characteroperand sign.

The exponent is added to the operand in response to the DUCMD 308 "Loadthe DU Exponent Register" command. An REXP register 730-138 is loadedfrom the ZADSP 3-11 signal bus. A ZEXP switch 730-140 selects theexponent bit configuration for an operand having 4-bit decimalcharacters and storing the least significant 4-bit character in an evendigit location in cache 750 through the ONE position of the ZEXP switch.All other exponents are selected through the 0 position of the switch.The signal ZEXP 0-8 output is applied to the 2 position of the ZSMRswitch ZSMR 730-180. The exponent character positions are selected bythe [2ZSMR 0-7 signal outputs from a control logic [2ZSMR 730-146. Thesignal is generated as follows. The boolean expressions for controlsignals [1ZSMR 0-7 and [2ZSMR 0-7 are shown supra.

The ASWC 5-6 output signals of the ASWC adder 730-68 indicate thelocation in the low order word of the operand of the low order characterfor 9-bit characters. Binary ONE is subtracted from this value in anACPE adder 730-74 to give the location of the high order digit of theexponent for an operand made up of 4-bit characters. A ZEMP switch730-120 selects the character position and the output signals ZEMP 1-3are applied to an EXPM shifter 730-122. The EXPM 0-7 output signals areapplied to the control logic [2ZSMR 730-146. The output signals [2ZSMR0-7 select the two adjacent character positions in the ZSMR switch730-180 to enable the exponent to be written into the low order word.

For a 4-bit operand it is possible for the most significant digitposition for the exponent character to be in digit position 7 and theleast significant position to be in digit position 0 of the next word.In this case the EXPM mask 730-122 generates a ONE output on the EXPM 7signal line when the ZEMP switch 730-120 pointer is at decimal 7 duringthe next to the last word received. When the last word is received theZEMP switch pointer remains at 7, the DBITS input signal is forced to aONE resulting in the EXPMO line being forced to ONE thereby activatingthe 0 character position of the least significant word.

The boolean expression for the DBITS signal is

DBITS=DFCO (DUCMD 303+FOPSTR) (ACPE1·ACPE2·ACPE3) D1EQFLP

Signals RDESC0 and RDESC1 are applied to the write select inputs ofRLNDO-3 register 730-12, RTNSO-3 register 730-32 and RCPO-3 registers730-42. Signals RDESC0 and RDESC1 are binary coded 00, 01 and 10 toidentify operands 1, 2 and 3 respectively.

Control signals [1ZLNDA and [2ZLNDA are applied to the ZLNDA switch730-16 and the ZTNSA switch 730-36. Status flag FMVN is applied to theZLNDB switch 730-20 and the ZTNSB switch 730-34.

Control signals [1ZCPA and [2ZCPA are applied to the ZCPA switch 730-44.The boolean expressions describing the signals are

[1ZLNDA=F3DESC·FLDCOMPL

[2ZLNDA=F3DESC·FLDCOMPL

[1ZCPA=FRDP1·FLDCOMPL+F3DESC·FLDCOMPL

[2ZCPA=F3DESC·FLDCOMPL

The ZSMR 0-35 output including decimal digits, exponents and sign areapplied to the ZDOD switch 730-152 and are loaded into the RDOD register730-154 for transfer to the cache 750.

In the short operand store the words are received from the executionunit 714 with the least significant word first and the most significantword last. A DUCMD 305 "Transfer Data from RCHO to RPK" command isinitiated by the firmware. The least significant word is received fromthe character unit 720 over the RCHU 4-35 signal bus and is stored inthe RPK register 730-162 through a buffer 730-168 and position 0 of theZPK 730-160 switch. If the short operand comprises 2 words then the mostsignificant word is placed in the RCHU register on the same cycle andappears over the RCHU 4-35 signal bus on the following cycle through thebuffer 730-168 position 0 of the ZPK 730-160 switch and is applied tothe input of a ZPKR switch 730-164 and a ZPKL switch 730-166 as signalsZPK 0-31. If the short operand was only one word long, zeros are placedon the RCHU bus to serve as the most significant word.

The negated output of the buffer 730-168, signals RCHU 4-35 is appliedto the input of an output zero and overflow detection logic 730-80 andthe effective digit logic 730-81. During the cycle in which the DUCMD305 is present the least significant word is tested for zero or overflowand the most significant word is tested for zero or overflow on thefollowing cycle which is marked by the FCZO flag being at logical ONE.

An RSCUM register 730-78 stores the operand 3 length plus scale factoroutput of the ZLNADJ switch 730-26. An RSCLM register 730-144 stores theoperand 3 scale factor output of the ASF adder 730-10. The outputs ofthe RSCUM and RSCLM registers input the logic unit 730-80.

The zero and overflow detection logic 730-80 masks out the non operand 3field and indicates to the firmware if the operand 3 field is zero sincethe DZERO output signal of detection logic 730-80 is at logical ONE inthat case and also masks out the operand 3 field and the scale factorfield and indicates to the firmware if there was a non zero decimaldigit in the character positions to the left of the most significantcharacter of operand 3 in the most significant word that is the DOFLoutput signal of detection logic 730-80 is at logical ONE. The RSCLM andRSCUM register outputs are used to mask out the non operand 3 characterpositions and, in addition the RSCUM register output masks out theoperand 3 and scale factor character positions thereby enabling theoverflow check.

The boolean expression for loading the RSCUM register 730-78 and theRSCLM register 730-144 is

[LDRSCM=(FLDCOMPL (FCRD+DUCMD 314+DUCMD 205) (DUCMD 305+FCZ0)) Theboolean expression for decrementing bit position RSCUM 0-6 and RSCLM 0-6is

[CNTDWNRSCM=(DUCMD 305+FCZ0)

A DUCMD 303 "Store Operand through Decimal Unit" command is initiated bythe firmware. Since this is a short operand operation, 2 words are sentfrom the execution unit 714 to the decimal unit 730 over the RCHU 4-35bus. The least significant word remains stored in the RPK register730-162 and the most significant word remains on the RCHU 4-35 bus forthe processing of the instruction.

The RRWC register 730-88 stores the internal location of the mostsignificant data word to be transferred from the decimal unit 730 tocache 750. The register is decremented each time a word made up of 4-bitcharacters is sent to cache 750. The register is also decremented eachtime a word made up of 9-bit characters is sent to an odd address incache 750. The boolean expression for the decrementing signal[CNTDWN-RRWC are described supra.

The RDSC register 730-58 stores the shift count which is applied to theZDS shifter 730-156 through the ZDSC switch 730-72.

Assuming the shift count is positive, i.e. the RDSC0 bit is a zero andthe RRWC register indicates a word count of greater than 1, then thezero outputs of the ZPKL switch 730-166 and ZPKR 730-164 are applied tothe shifter 730-156. The ZDS 0-31 output signals are zero and areapplied to the ZID switch 730-150. The ZID 0-35 output signals areapplied to the ZSMR switch 730-180 where the rewrite characters andleading sign may be added to the most significant word. The ZSMR 0-35output is applied to the ZDOD switch where for 9-bit character words,EBCDIC or ASC11 zone characters are added and the ZDOD 0-35 outputsignals loaded into the RDOD register 730-154 for transfer to cache 750.Control signal [$RDODA at logical ONE loads the RDOD register 730-154.The boolean expression is

[$RDODA=((FDATA-AV+DUCMD 203+DUCMD 310+DUCMD 309+FRPK·DUCMD303+FRPK·FALT·FSWRT)·DUCMD 311)

When the count in the RRWC register 730-88 equals ONE then the mostsignificant word stored in the RCHO register 720-10 and appearing on theRCHU 4-35 signal bus is applied through the buffer 730-168 throughposition 0 of the ZPK switch 730-160, through position 0 of the ZPKRswitch 730-164, through the ZDS shifter 730-156 where it is shifted tothe right the number of digit positions equal to the ZDSC 1-3 binaryshift count. Zeros equal in number to the shift count are inserted tothe left of the most significant digit position. The ZDS 0-31 outputsignals are switched through position 0 of the ZID switch 730-150. Theoutput signals ZID 4-35 are applied to the ZSMR switch for 4-bitcharacters where the word is expanded from 32 to 36 bit positions. TheZSMR 0-35 output signals are switched through position 3 of the ZDODswitch 730-152 to the RDOD register 730-154 from which the word istransferred to cache 750.

If the word comprises 9-bit characters, then the ZID 0-35 output signalsare applied to position 2 of the ZDOD switch 730-152 if the word iswritten in an even address in cache 750 or applied to position 1 of theZDOD switch 730-152 if the word is written in an odd address in cache750 through the RDOD register 730-154. Assuming a word to an evenaddress in cache 750. Then the ZID 4-35 is switched through position 2of the ZDOD switch 730-152 where the 4 characters indicated by ZID 4-19are expanded to 36 bits by adding the EBCDIC or ASCII zone characters.On the next cycle the ZID 4-35 signals are switched through position 1of the ZDOD switch where the ZID 20-35 signals are expanded to 36 bitsby adding the EBCDIC or ASCII zone characters.

The RRWC register 730-88 is decremented each time a 4-bit character wordis transferred to cache 750 or each time a 9-bit character word istransferred to an odd address in cache 750. The RRWC counter 730-88 isdecremented to zero with the shift count ZDSC 1-3 a positive binarynumber. In this case the ZPK 4-31 output signals are applied through theZPKL switch 730-166 and the RPK 0-3 output signals are applied throughthe ZPKR switch 730-164 and the second word is processed as before.

The RRWC register 730-88 is decremented to binary -1 with the shiftcount ZDSC 1-3 a positive number. The RPK register 730-162 storing theleast significant word has its RPK 0-31 output signals applied throughthe ZPKL switch 730-166 to the ZDS shifter 730-156. Zeros were appliedto the ZDS shifter 730-156 through the ZPKR switch. The ZDS 0-31 outputsignals are applied through the switches to load the RDOD register730-154 for transfer to cache 750.

If required the RRWC register 730-88 is decremented to binary -2. Zerosare applied to the ZDS shifter 730-156 inputs. This cycle of operationenables the exponent of trailing sign and also replacement characters tobe stored in the RDOD register 730-154 after being switched through theZEWR switch 730-180 and the ZDOD switch 730-152.

Each of the above store operations is enabled by the DUCMD 303 signalset by a firmware command to load the word in the RDOD register 730-154on a first firmware cycle and to write the word in cache 750 on a secondfirmware cycle. The first and second firmware cycles are repeated untilall of the words containing operand 3 information are transferred tocache 750.

The sequence of steps for loading cache 750 for a negative shift count,i.e., the RDSC0 output signal is equal to ONE, is the same as for thepositive shift count with the exception that the binary value in theRRWC register 730-88 at each step is one more than its correspondingvalue for the positive shift count.

As a part of the long operand store operation the firmware initiates aDUCMD 304 "Check Zero/Overflow" operation. Operand 3 information is sentfrom the execution unit 714 to the decimal unit 730 under firmwarecontrol a word at a time starting with the least significant word. ADUCMD 304 command is issued for each significant word to be check andthe word is put into the RCHO register 720-10, FIG. 2, at the same time.The last DUCMD 304 command is issued by the firmware for the mostsignificant word of the long operand. The decimal unit 730 scans eachword received on the cycle following the DUCMD 304 command which ismarked by the FCZ0 flag being set from the least significant word tomost significant word, counting the number of digits to the right of,and including the most significant digit. This count is stored in theRWPC register 730-84, RLZC1 register 730-96, and RLZC2 730-98. Theoutput of these registers is available to the firmware in response to aDUCMD 311 "Put Operand Word Count into RDOD" command.

Effective digit logic 730-81, FIG. 7, examines the resultant operandword RCHU 4-35, received from the character unit 730. The resultantoperand word was generated in the execution unit 714 and is the resultof the decimal numeric operation performed on operand 1 and operand 2.

The negated signals RCHU 4-35 are applied to the inputs of NAND gates81-2 through 81-16. Decimal digit 0 signals RCHU 4-7 are applied to theinput of NAND gate 81-2. Decimal digit 1 signals RCHU 8-11 are appliedto the input of NAND gate 81-4. In a similar manner the decimal digit2-7 signals are applied to the inputs of NAND gates 81-6 through 81-16.

If the inputs to NAND gate 81-2 indicate that digit position 0 signalsRCHU 4-7 indicates a digit which is not zero, then the DGZ-0 outputsignal of NAND gate 81-2, at logical ONE, is applied to the input of aNAND gate 81-42. The output signal EDC-0 at logical ONE indicates thatthe word contains eight significant digits. The output signal DGZ0, atlogical ZERO, is applied to the inputs of NAND gates 81-44, 81-46 and81-48 thereby forcing the output signals EDC1-3 to logical ZERO.

If the digit 0 signal RCHU 4-7 indicates a decimal zero, then the outputof NAND gate 81-42 is disabled and the output of NAND gates 81-44, 81-46and 81-48, which indicates the position of the most significant digit ofthe operand word, is enabled. Assume that the most significant digit isin position 5 of the 8 position operand word positions 0 through 7.Therefore the DGZ5 output of NAND gate 81-12 is at logical ZERO and theDGZ 0-4 outputs of NAND gates 81-2, 81-4, 81-6, 81-8 and 81-10 are atlogical ONE.

Digit 5 signal, at logical ZERO, is applied to the input of NAND gates81-22 and 81-32. The output signals DZR56 and DZR5/7 at logical ONE areapplied to the inputs of NAND gates 81-28, and 81-40 respectively. Theother inputs, signals DZR 34 and DGZ4 at logical ONE are applied to theother inputs of NAND gates 81-28 and 81-40 respectively. The outputsignal DZR3/6 at logical ONE is applied to the input of a NAND gate81-36. The other input, signal DZR12 at logical ONE forces the outputsignal DZR1-4 of NAND gate 8-34 to the logical ZERO, thereby forcing theoutput of NAND gate 81-44, signal EDC-1 to logical ZERO. The output ofNAND gate 81-36, signal DZR1/6 is at logical ZERO since the input signalDZR34 of NAND gate 81-28 is at logical ONE. This forces the outputsignal DZR1/6 to logical ONE forcing the output of NAND gate 81-46,signal EDC-2 to logical ONE.

The output of NAND gate 81-40 signal DZR4/7 at logical ZERO is appliedto the inputs of NAND gate 81-24. The output signal DZR3/7 at logicalONE is applied to the inputs of a NAND gate 81-30. The other inputsignal DGZ-2 at logical ONE forces the output signal DZR2/7 to logicalZERO thereby forcing the output of a NAND gate 81-38, signal DZR1/7 tological ONE. This forces the output of NAND gate 81-48, signal EDC-3 tological ONE.

Signals EDC-1, at logical ZERO, EDC-2 and EDC-3 at logical ONE, indicatethat there are 3 significant digits in the operand word.

The least significant word is received by the decimal unit 730 over theRCHU 4-35 signal bus into the buffer 730-168. The negated output signalsRCHU 4-35 are applied to the effective digit logic 730-81. The effectivedigit logic 730-81 output signals EDC 0-3 are applied to the input ofthe ZEDC switch 730-82. The ZEDC 1-3 output signals represent a binarycount of the significant digits in the word starting from the mostsignificant digits and counting to and including the low order digitsposition 7. The ZEDC 0 output signal at a logical ONE, indicating thatthe most significant position of the word, position zero, contains adecimal digit which is not a zero, is loaded into the AEDC adder 730-96after the first word is received and the RWPC register 730-84 isincremented by ONE each time a subsequent word is received from theexecution unit 714 by control signals [ENRWPC, [CNTUP-RWPC and [LDRWPCbeing applied to the input terminals of the RWPC register 730-84.

Boolean expressions for control signals [LDRWPC which loads the RWPCregister 730-84 and [ENRWPC which enables the output of the register areas follows:

[ENRWPC=((DUCMD 305+FCZ0)+FCRD·DUCMD 314·DUCMD 205)

[LDRWPC=((DUCMD 305+FCZ0) (FCRD+DUCMD 314+DUCMD 205))

The RWPC 0-3 output signals are applied to one terminal of an AEDC adder730-86. The ZEDC0 signal is applied to another terminal of the AEDCadder 0-3 whose output is switched through the ZEDD switch 730-94 andstored in positions 0-3 of RLZC1 register 730-96 and RLZC2 register730-98 whenever the received word has a non zero decimal digit stored.The ZEDC 1-3 binary output signals of the ZEDC switch 730-82 whichindicates the number of significant digits in the word are stored inpositions 4-6 of the RLZC1 register 730-96 and the RLZC2 register730-98. The register outputs signals RLZC1 0-6 and RLZC2 0-6 are appliedto the ZLZC switch 730-76, whose output is available to the firmwarethrough position 3 of the ZID switch 730-150. The RLZC1 and RLZC2registers both store the number of significant digits in operand 3. Whenthe first word is received from the execution unit 714, assumingposition 0 contains a decimal digit, not zero, the binary quantity 8 isstored in the RLZC1 and RLZC2 registers. The ZEDC0 signal input to theZEDC adder 730-84 is a logical ONE. When the second word is receivedagain assuming position 0 contains a decimal digit, then the ZECD0signal input to the ZEDC adder is at a ONE and the RWPC3 signal input isat a one. This forces the ZEDC 0-3 output to a binary 2 and the quantitybinary 16 is stored in the RLZC1 and RLZC2 registers. Assuming the thirdword contains only 3 decimal digits with the most significant digit inposition 5 then the ZEDC 0-3 will store a binary 011 in the RLZC1 andRLZC2 registers 730-96 and 730-98 respectively which will now have thequantity 19 stored in the registers.

The RLZC1-2 and RLZC2-2 bits (binary 16 bit) are again set since theAEDC 0-3 output is at binary 2. The RWPC 730-84 register was incrementedfrom binary ONE to binary TWO. The RRWC register 730-88 stores theadjusted length of the operand which is calculated from length and scalefactor values, as designated by the descriptor. The RWPC register 730-84stores the number of words examined by the firmware as the result of theDUCMD 304 on a long operand.

In the long operand store operation it is necessary to compare operand 3which is the result of the operand 1 and operand 2 calculations, as itexists internally in the execution unit 714 with the operand 3 as it isto be stored in cache 750, and to do so with a simplified firmwareprocedure.

Initially, the firmware issues the DUCMD 303 "Store Operand Thru DU"command. This command initiates the actual store sequence in the decimalunit 730. Unlike the short operand store procedure, the firmware willnot prepare a write address and send a write command to cache 750 untilit is permitted to do so by the decimal unit 730. The decimal unit 730makes this decision based on the information stored in the RRWC register730-88, the RWPC register 730-84 and the position of the mostsignificant digit within the word when the operand is received by thedecimal unit 730 from the execution unit 714 as indicated by the outputof the ACPNB adder 730-50. As in the short operand case the output ofthe ACPR adder 730-62 is subtracted from the output of the ACPNB adder730-50 in the ACPSC adder 730-54 to generate the shift count which isstored in the RDSC register 730-58.

It should be noted that every word stored in cache 750 requires 2firmware cycles minimum for the store operation. The address in cache750 in which the operand word is written is sent to cache 750 on thefirst cycle and the data to cache 750 is sent on the second cycle. Thefirmware therefore is organized in 2 step loops, the first stepgenerates the address and the write command and the next step passes thedata through from the decimal unit 730 to cache 750. The process startson the cycle the firmware sends the DUCMD 303 command to the decimalunit 730. The firmware examines the start write signal RRLTRD to theexecution address and branch circuits 701-1, FIG. 4, for logical ONEwhich indicates that a write command should be generated and issued tothe cache 750.

The FSWRT flag is set to indicate to the decimal unit 730 that thefirmware is sending write commands to cache 750. If the start write lineRRLTRD is at logical ZERO then the firmware controls the loading of theRCH0 register 720-10 of the character unit 720 with words from theexecution unit 714 until the most significant word is stored. This isthe case where the count in the RWPC register 730-84 would be greaterthan the count in the RRWC register 730-88. The RWPC register 730-84 isdecremented each time a word is placed in the RCH0 register 720-10 untilthe count in the RWPC register equals the count in the RRWC register ifthe RDSC register 730-58 indicates a positive shift or until the countin the RWPC register is less than the count in the RRWC register if theRDSC register indicates a negative shift. For a positive shift the mostsignificant word is stored in the RCH0 register 720-10. For a negativeshift the most significant word is stored in the RPK register 730-162and the second word is stored in the RCH0 register 720-10.

For the positive shift operation, the start write line RRLTRD is forcedto logical ONE and the firmware initiates a write into cache 750 loopwhen the RRWC register 730-88 count equals the RWPC register 730-86count. This sets the FSND flag which strobes the previous word stored inthe RCH0 register 720-10 into the RPK register 730-162 and indicates tothe firmware to load the next word into the RCH0 register 720-10 fromthe execution unit 714 by forcing the send data signal RREQRD to logicalONE.

The boolean expressions for the start write signal RRLTRD and the senddata signal RREQRD for long operand store operations are as follows:

DSEND DATA=(FCPC0·ZTNSA0+ZTNSA0)·DMSEQ·FSWRT.multidot.FMSDRN

DSTRTWRT=FMSEQ·DMSDRGTE·RDSC0+DMSDRGTE·RDSC0+DUCMD 303·RRWC0

RREQRD=FDUACT·DSEND DATA·DUCMD 202·DUCMD 204·DUCMD 306

RRLTRD=FDUACT·DSTRT-WRT·DUCMD 202·DUCMD 204

DMSDRGTE=(RWPC 0-3·MINUS·1)>(RRWC0·(RRWC1+RRWC2)·RRWC3·RRWC4 RRWC5·RRWC6

DMSEQ=(RWPC 0-3·MINUS·1)=(RRWC0·(RRWC1+RRWC2)·RRWC3·RRWC4·RRWC5·RRWC6

DMSDRGT=(RWPC 0-3·MINUS·1)>(RRWC0·(RRWC1+RRWC2)·RRWC3·RRWC4·RRWC5·RRWC6)

The boolean expressions for the count down of the RWPC register 730-84are as follows:

[CNTDWN-RQPC=FRPK·DUCMD 303·(ZTNSA0·FCPC0+ZTNSA0)+FRPK·(FOPSTR+DUCMD303·DMSDRGTE)·FALT·(FSWRT·DMSDRGT+(ZTNSA0·FCPC0+ZTNSA0)·FSWRT·DMSDRGT))

[$RDOD=FDATA-AV+DUCMD 203+DUCMD 310+DUCMD 311+DUCMD 309+FRPK·DUCMD303+FRPK·FALT·FSWRT

The decimal unit 730 compares the RRWC 0-6 output signals with the RWPC0-3 output signals in a comparator 730-90. The comparator output signalsDMSEQ, DMSDRGT and DMSDRGTE condition the register and switch control730-91 for generating the RRLTRD and RREQRD signals and the varioussignals controlling the ZPK switch 730-160, the RPK register 730-162,the ZPKL switch 730-166 and the ZPKR switch 730-164. The signals alsocondition the status flag control logic 730-202 for setting the FSND,FSWRT, FMSDRGTE and FMSEQ flags as well as decrementing the RRWCregister 730-88 and the RWPC register 730-84. When the number of wordsstored in the RRWC register 730-88 is greater than the number of wordsstored in the RWPC register 730-84 then the cache write flag FSWRT isset but the FSND flag is not set. This results in the RDOD register73-154 outputting words containing all zeros to cache 750 anddecrementing the RRWC register 730. When the comparator 730-90 indicatesan equal condition, the FSND flag is set and under firmware control themost significant word is sent from the execution unit 714 to the decimalnitu 730 over the RCHU 4-35 signal bus thereby inputting the buffer730-168. The buffer 730-168 output is applied to the 0 position of theZPK switch 730-160. The most significant word is stored in the RPKregister 730-162 from the ZPK switch 730-164. Control logic, not shown,enables the ZPKR switch if a data word can be assembled and sent tocache 750. In that case, the ZPKR 0-31 output signals are applied to theZDS shifter 730-156 and the word shifted by a number of digit positionsequal to the binary value of the ZDSC 1-3 signals. Zeros are applied onthe ZPKL 4-31 signal bus. The ZDS 0-31 output signal is switched throughposition 0 of the ZID switch 730-150 to position 0 of the ZSMR switch730-180 if the operand comprises 4-bit characters. If the operandcomprises 9-bit characters then the ZDS 0-31 output signal is switchedthrough position 0 of the ZID switch 730-150 to position 1 of the ZDODswitch 730-152 if the word is to be written in an odd address in cache750 or to position 2 of the ZDOD switch if the word is to be written inan even address in cache 750.

Position 0 of the ZSMR switch expands the word containing 4-bit digitsfrom 32 bits to 36 bits after which the word is switched throughposition 3 of the ZDOD switch 730-152 to the RDOD register 730-154 whereit is stored and sent to cache 750 on the next cycle.

Position 2 of the ZDOD switch 730-152 expands words of operands to bemade up of 9-bit digits by expanding the ZID 4-19 output signals togenerate the 36-bit word by adding the ASCII or EBCDIC zone characters.Position 1 of the ZDOD switch 730-152 expands the ZID 20-35 outputsignals to the 36-bit ZDOD 0-35 signal bus. The ZDOD 0-35 output signalsfrom position 2 of the ZDOD switch are stored in the RDOD register730-154 and transferred to an even cache 750 address. The position 1outputs of the ZDOD switch are transferred to odd cache 750 addresses.

In the event that the comparator 730-90 output indicates that the RRWC0-6 binary count of the RRWC register 730-88 is less than the RWPC 0-3binary count of the RWPC register 730-84 then data words are neitherreceived from the execution unit 714 nor sent to cache 750 by thedecimal unit, and the RWPC register 730-88 counts down until the outputof the comparator 730-90 indicates that the RWPC 0-3 binary count equalsthe RRWC 0-6 binary count. This sets the FMSEQ, and FSWRT flags and thedata words are clocked into the RDOD register 730-154 and transferred tocache 750.

Operands having 9-bit characters transfer 2 words to cache 750 for everyword received from the execution unit 714 during normal operation. Theword received from the execution unit 714 has up to eight decimal digitsof 4-bits each and is expanded to 2 words, each containing up to 4decimal digits of 9-bits each. The FCPC0 flag cycling on and offcontrols the transferring of words to odd addresses and to evenaddresses in cache 750.

Cycle Delay

The processing of short operands is speeded up by predicting, as theprocessing of the instruction is starting, the number of words sent fromthe decimal unit 730 to the execution unit 714 and the number of cyclesbetween the time the first read command is sent to the cache 750 and thefirst data word is sent to the execution unit 714. The number of wordsand cycles of delay are calculated in the decimal unit 730 and sensed bythe firmware in the execution control unit 701. The decimal unit 730output signals, PK-VCTR 0-3, FIG. 4, are applied to the executionaddress and branch circuits 701-1 and cause the firmware to branch to aparticular address in the execution control store 701-4 which results inthe firmware executing a subroutine to process the operand. Theparticular subroutine selected is designed to process the exact numberof words of the operand with the exact number of cycles of delay therebyprocessing the operand with minimum of number of microwords.

The calculation for the number of delay cycles is a function of the typeof data, that is, whether the incoming operand is made up of 4-bit or9-bit characters, the location of the most significant character in theoperand coming from cache 750 and the location of the most significantdigit in the operand being transferred to the execution unit 714. As anexample, assume an 8-decimal digit operand made up of 9-bit characterswith a leading sign. Also assume the sign was in the third characterposition of the first word of the operand. The second word from cache750 contains 4-decimal characters and the third word from cache 750contains 4-decimal characters. The decimal unit 730 would not load anydecimal digits upon receiving the first word since the first word onlycontained the sign. Four decimal digits were received from the secondword, still not enough to fill the RDOD 730-154 register. Four decimaldigits were received from the third word and the RDOD register wasloaded with 8-decimal digits.

This load operations took 3 cycles to assemble and transfer the word tothe execution unit 714. The PK-VCTR 0-3 signals lines would indicate aone word transfer with a 2 cycle delay to the firmware. The firmware byusing the information indicating the number of words transferred and thenumber of cycles of delay performs the control of transferring datawords from one register to another on a specific cycle rather than tohalt or loop waiting for the data word.

The delays are a function of the data type, 4-bit or 9-bit decimalcharacters as indicated by the condition of the output of the ZTNSAswitch 730-36 and the ZTNSB switch 730-34, ZTNSA0 or ZTNSB0 signals. TheACPNB adder 730-50 gives as an output the digit position of the mostsignificant digit of the word received from cache 750. The ACPDF adder730-52 gives the difference in positioning between the first characterposition for the high order digit in the first word from cache 750 andthe digit position of the most significant digit as it is transferred tothe execution unit 714. The output of the ZCPA switch 730-44 signalZCPA0 identifies the word from cache 750 as being from an odd or evenword address.

The Boolean equations for the number of words and cycle delaycalculations are readily interpreted into functional hardware by one ofordinary skill in the art and are as follows:

PK-VCTR φ=φ

PK-VCTR 1=TDBφ

PK-VCTR 2=TDB1

PK-VCTR 3=ARWC6

TDBφ=[(ZTNSAφ·FDUACT·FRDP1+ZTNSBφ·FRDP1)(ACPDFφ·ZCPAφ+ACPDFφ·ZCPAφ·ACPDF1)]

TDB1=[(ZTNSAφ·FDUACT·FRDP1+ZTNSBφ·FRDP1) (ACPDFφ)+(ZTNSAφ·FDUACT·FRDP1+ZTNSBφ·FRDP1) [(ACPDFZ·ZCPAφ)+(ACPDFφ·ZCPAφ(ACPNBφ·ACPNB1·ACPNB2·ACPNB3+ACPDF1.multidot.ACPNBφ·ACPNB1)+ACPDFφ·ZCPAφ·ACPDF1)]]

The PK-VCTR 1 signal forced to binary ONE indicates a 2 cycle delay. ThePK-VCTR 2 signal forced to binary ONE indicates a 1 cycle delay. ThePK-VCTR 3 signal forced to binary ZERO indicates that 1 data word willbe transferred to the execution unit 714 from the decimal unit. ThePK-VCTR 3 signal forced to binary ONE indicates that 2 data words willbe transferred to the execution unit 714.

For the PK-VCTR 1 calculation the ZTNSAφ·FDUACT·FRDP1 Boolean expressionindicates a 9-bit operand 1 word from cache 750. The ZTNSBφ·FRDP1indicates a 9-bit operand 2 word from cache 750. The ACPDFφ·ACPAφexpression indicates a left shift through the shifter 730-156 of theword from an even cache 750 address. The ACPDFφ·ZCPAφ·ZCPDF1 expressionindicates a left shift of from 1-3 decimal digits of a word from an oddcache 750 address.

For the PK-VCTR 2 calculation ZTNSA0·FDUACT·FRDP1·ACPDFφ indicates a4-bit operand 1 word from cache 750 requiring a left shift through theshifter 730-156. ZTNSB0·FRDP1·ACPDFφ indicates a 4-bit operand 2 wordrequiring a left shift. ZTNSAφ·FDUACT·FRDP1+ZTNSBφ·FRDP1 indicates a9-bit operand 1 word and a 9-bit operand 2 word.

ACPDFZ·ZCPAφ+ZCPDFφ·ZCPAφ indicates either a zero shift or a right shiftof the word from the even cache address. ACPNBφ·ACPNB1·ACPNB2·ACPNB3indicates that the high order decimal digit is in position 4 of the4-bit character word or position zero of the 9-bit character word fromodd cache address. ACPDF1·ACPNBφ·ACPNB1 indicates that the high orderdecimal digit received from cache 750 is in locations 1-3 and the shiftcount is less than 4 digits. ACPDFφ·ZCPAφ·ACPDF1 indicates a left shiftof greater than 3 digit positions from the odd cache address word. Notethat the ACPDFZ signals at binary ONE indicates that the adder 730-52 isset a binary ZERO. For the PK-VCTR 3 calculation, ARWC6 indicates a oneword transfer from the decimal unit 730 and the execution unit 714 whenat binary ZERO and a two word transfer when at binary ONE.

Decimal Unit 730--FIG. 3--Rewrite Operation

Operand 3 may start and end in character positions within the mostsignificant word and the least significant word. It may be necessary toretain the information stored in the most and least significant words ofoperand 3 that are not part of operand 3. In this case, the firmwareinitiates a DUCMD 306 "Load Rewrite Data" command in the decimal unit730 to load the most significant word into the REWR2 register ofregister bank 730-177 through the ZDI 0-35 bus from cache 750, the RDIDregister 730-158 and the RDID buffer 730-176. The firmware initiates asecond DUCMD 306 to load the least significant word in the REWR3register of the REWR 0-3 register bank 730-177. When the firmwareinitiates a DUCMD 303 "Store Operand Through Decimal Unit" command themost significant word appears on the ZID 0-35 signal bus. Assuming 4-bitdecimal characters for the operand the RCP2 register of register bank730-42 stores the starting character position of the operand 3. Sincethis is a descriptor 3 operation the RCP2 position of switch 730-44 isselected and the ZCPA 0-3 output signal is applied to a ZRUMP switch730-148. Position 1 of the ZRUMP switch is activated and the ZRUMP 0-2output signal is applied to an REWUM shifter 730-149. The REWUM 0-7output signals are applied to control [1ZSMR logic 730-142 and control[2ZSMR 0-7 output signals select the digit positions of the ZSMR switchthat will be selected. For example, for processing the most significantword of the 4-bit digit operand, digit positions in position 0 of theZSMR switch 730-180 would be selected for the operand digit data. Thesign position in position 1 of the ZSMR switch 730-180 would be selectedif the operand had a leading sign and the digit positions to the left ofthe operand would be selected in position 3 of the ZSMR switch for therewrite data. The REWUM 0-7 signal output of the shifter 730-149 is azero for those digit positions requiring write data. The ZSMR 0-35output bus is switched through position 0 of the ZDOD switch 730-154 tothe RDOD register 730-154.

If the operand contains 9-bit decimal digits then the [1ZSMR 0, 2, 4 and6 logic signals and [2ZSMR 0, 2, 4 and 6 logic signals are applied tothe unpack ZDOD logic 730-184. The [1ZDOD 0-3 and [2ZDOD 0-3 outputsignals enable the rewrite and leading sign digit positions of switchposition 3 and the operand decimal digit positions of either position 1or position 2 of the ZDOD switch 730-152.

During the load operation for a 2 descriptor operation the mostsignificant word of operand 2 which could contain rewrite information iswritten into the REWRO register of the register bank 730-177 and allsubsequent words are written into the REWR1 register replacing theprevious word. This results in the most significant word of operand 2stored in the REWR0 register and the least significant word of operand 2stored in the REWR1 register. The loading of these registers into theRDOD register 730-154 is as described supra.

The REWR register bank 730-177 is enabled by the control signal [$REWR.The boolean expression is [$REWR=(FDID+FLDREWRH).

Control signal [WRREWR1 is applied to terminal 1 and status flagFLDREWRH is applied to terminal 2 of the register select input terminalsto select one of four registers REWR 0-3. The boolean expression controlsignal [WRREWR1 is:

[WRREWR1=FOP2LD·FOP2F+FLDREWRH·FREWR

The output of registers REWR 0-3 is selected through the ZEWR switch730-178. Signal [1ZEWR is applied to output select terminal 1 and statusflag FREWR is applied to the output select terminal 2 of ZEWR switch730-178. The boolean expression for control signal [1ZEWR is:

[1ZEWR=(FREWR·FREWR2·FFOSD+FOP2S·FFOSD·FREWR).

Decimal Unit 730--FIG. 3--Rounding Constant

Two DUCMD 309 "Put the Rounding Constant into RDOD" commands areinitiated by the firmware. For short operands the rounding constant issent to the execution unit 714 in response to the first DUCMD 309 if theconstant is to be inserted in the least significant word. The roundingconstant is sent to the execution unit in response to the second DUCMD309 if the constant is to be inserted in the most significant word. Foreither case, a word of all zeros is sent to the execution unit for theother DUCMD 309 command. The other rounding constant, binary 5, is addedto the position to the right of the scale factor pointer (decimalpoint). The rounding constant is stored in bit positions 4-7 of switchposition 3 of the ZPK switch 730-160.

The ATMP adder 730-30 subtracts a ONE from the operand 3 scale factorstored in the RSF2 register of register bank 730-4 and is applied to theATMP adder 730-20 through the ZASFB switch 730-28. If the ATMP6 outputsignal is a ZERO then the rounding constant is applied to the leastsignificant word in response to the DUCMD 309 command. If the ATMP6output signal is a ONE then the rounding constant is applied to the mostsignificant word in response to the second DUCMD 309 command.

The ATMP 7-9 output signals are inverted by inverter 730-147. The ATMP7-9 output signals are selected by the ZDSC switch 732 and provide thebinary shift count to the shifter 730-156.

The ZPKR switch 730-164 is enabled in response to the first DUCMD 309command if the rounding character is added to the least significant wordand enabled in response to the second DUCMD 309 command if the roundingcharacter is added to the most significant word. In either case thebinary 5 output from position 3 of the ZPK 730-160 switch is transferredto the execution unit 714 through the ZPKR switch 730-164, the ZDSshifter 730-156, position 0 of the ZID switch 730-150, position 0 ofZDOD switch 730-152 and the RDOD register 730-154.

In the long operand store operation the decimal unit 730 responds to thefirst DUCMD 309 command with a pointer to the word in scratchpad towhich the rounding constant is added and responds to the second DUCMD309 command with the rounding constant. The ATMP 0-6 output signalswhich indicate the word to which the rounding constant is added areselected through position 3 of the ZLZC switch 730-76, position 3 of theZID switch 730-156, position 0 of the ZDOD switch 730, the RDOD register730-154 to the execution unit 714. The rounding constant binary 5, istransferred to the execution unit 714 during the second DUCMD 309operation as in the short operand above.

Sign Extraction

As each operand is received by the decimal unit 730 during the loadoperation the sign character is examined if it is not an overpunchedsign character. The decimal unit 730 verifies that it is a legal signcharacter.

An RCPS 0-2 register 730-126 stores the character location within theword of the sign character. A ZCPS switch 730-124 selects the positionof the sign character. The ZCPS switch position 0 identifies the leadingsign position for 9 bit character operands. Switch position 1 identifiesthe leading sign position for 4-bit character operands. Switch position2 identifies the trailing sign position for 9-bit character operands.Switch position 3 identifies the trailing sign position for 4-bitoperands.

The RCPS 0-1 output signals select the position of a ZCH switch 730-170that could contain the sign character. No attempt is made to select thetrailing or leading word of the operand in the ZCH switch 730-170. Anoperand word received from cache 750 over the ZDI 0-35 signal bus isstored in the RDID register 730-158 and is applied to the ZCH switch730-170. The ZCH 1-8 output signal is applied to a ZCHL switch 730-172and to sign extraction logic 730-174. Position 1 of the ZCHL switch isselected for 9-bit operands and 4-bit operands having an odd characterpointer.

The sign extraction logic 730-174 selects either the sign character fromthe trailing word or from the leading word. If the sign character iscoded as an illegal character than a SET ILLEGAL logic signal forces afault indication for the software. If the sign character is coded as acorrect sign then the SET SIGN logic signal sets an indication for thesoftware. The ZCH 1-8 output signals to the sign extraction logicindicate 8-bit EBCDIC sign characters. The ZCH 1-8 output signals to theZCHL switch indicate 4-bit sign characters in the lower half of the9-bit character (bit position 4-8) position for 9-bit characteroperands. For 4-bit operand words, even pointers indicate the left4-bits (bit positions 1-4) and odd pointers indicate the right 4-bits(bit positions 5-8).

Control signals [1ZCPS and [2ZCPS are applied to the terminals 1 and 2select inputs of ZCPS switch 730-124. The boolean expressions are:

[1ZCPS=(ZTNSA0·FDUACT·FRDP1+ZTNSB0·FRDP1)

[2ZCPS=(ZTNSA1·ZTNSA2·FDUACT·FRDP1+ZTNSB1.multidot.ZTNSB2·FRDP1)

The RCPS register is enabled by a [$RCPS control signal whose booleanexpression is:

[$RCPS=(FDUACT·FRDP1)+SFOP2LD)

Overpunch Digit Correction--FIG. 3

Operands made up of words having 9-bit characters may have separatesigns in either a leading or trailing character position or the operandmay have a sign included in the decimal digit code in a single characterposition. This requires that a correction be made to the decimal digitto include the overpunched sign. Assume that operand 1 requires anoverpunched sign correction. An ROP1 logic signal is sent from thecontrol store 704-2 to the decode logic 730-38. If the ZTNSA 0-2 outputsignal from the RTNS2 register of register bank 730-32 and the ZTNSAswitch 730-36 is coded to a binary 000 or 011 indicating 9-bitcharacters with leading sign or trailing sign, a D1EQOVP logic signaloutput decode logic 730-38 is forced high. The D1EQOVP logic signalselects the 1 position of a ZSSC switch 730-108 for a trailing signoperand. The 0 position of the ZSSC switch is selected for the leadingsign. The RLMP 4-6 signals are coded to point to the character positionof the leading sign and the RTMP 4-6 signals are coded to point to thecharacter position of the trailing sign.

The ZSSC 0-2 shift count signals are applied to a shifter 730-145 toshift a DBITT logic signal the number of bits specified by the ZSSC 0-2count. The DBITT logic signal is forced to a ZERO for the overpunchedsign operations during the cycle in which the most significant word orthe least significant word is read from cache 750 for the leading signor trailing sign correction respectively. The shifter 730-145 outputsignals ZCRDGM 0-7 are applied to the ZID switch control logic 730-188to select position 2 of the ZID switch for the character position thatis indicated by the one signal of the ZCRDGM 0-7 signals that is at aZERO which points to the overpunched sign position.

The RSGN register 730-134 is loaded with the corrected overpunched signcharacter for operand 1 under firmware control. The REXP register730-138 is loaded with the corrected overpunched sign character foroperand 2 under firmware control. A ZCRDG switch 730-136 selects theRSGN 5-8 output signals for the operand 1 overpunched sign correctioncharacter. The ZCRDG 0-3 signals are inverted by an inverter 730-186 andare applied to position 2 of the ZID switch 730-150. When the word towhich the corrected overpunched sign is added is received from cache 750and is switched through the decimal unit 730 to be stored in the RDODregister 730-154. The character in the sign position is replaced by theACRDG 0-3 corrected overpunched sign character.

The boolean expression for the DBITT signal is:

DBITT=(FOP1LD·D1EQOVP·(ZTNSA1·FFD0+ZTNSA(1).multidot.DMPEQ)+FOP2LD·D2EQOVP·(ZTNSB1·FFD0+ZTNSA(1)·DMPEQ))

where DMPEQ is at logical ONE when the contents of the RLMP register730-102 equals the contents of the RTMP register 730-100.

The above equation indicates that the DBITT signal is set to logicalZERO when operand 1 or operand 2 requires an overpunched sign correctionduring the load operation. ZTNSA1·FFD0 indicates a leading overpunchedsign and ZTNSA1·DMPEQ indicates a trailing overpunched sign.

D1EQOVP=(DBITX·ROP1·ZTNSA0)

D2EQOVP=(DBITZ·ROP1·ZTNSB0)

During the store operation the sign character is placed in the RSGNregister 730-134 and inserted in the operand word through position 1 ofthe ZSMR switch 730-180 as previously described.

Decimal Unit 730--FIG. 3--Load STC Mask into RDOD

The firmware initiates a DUCMD 203 Load STC Mask into RDOD commandduring the Store Character in Accumulator and Quotient RegisterInstructions (STCA and STCQ). The decimal unit 730 receives the RCHU30-35 output signals from the character unit 720 which are applied toposition 1 of the ZID switch 730-150 through the buffer 730-168. Each ofthe RCHU 30-35 output signals at a ONE results in the corresponding 6bits of position 1 of the ZID switch 730-150 being forced to a ONE.These groups of 6 bits are stored in the RDOD register 730-154 throughthe ZDOD switch 730-152.

FIG. 4 shows the relationship between the decimal unit 730 hardware andthe firmware in the execution control store 701-2. The execution addressand branch circuits 701-1 send the control store address locations ZECSA0-12 to the execution control store 701-2. The microword at that addresslocation is read out and bit positions RSCR 88, 89, 94-97 input adecimal unit 730 decode logic 730-204 which consists of conventionaldecode logic circuitry. Table 1 shows the RSCR 88, 89, 94-97 bitconfigurations for the respective DUCMD 200-206, 300-315 commands.

The DUCMD 200-206 300-315 commands input a status flag control logic730-202. This unit is made up of conventional flops set and reset in aconventional manner.

The I cycle control state circuits 704-102 described in theaforementioned application Ser. No. 853,944 generates the FPOA [POPHOLDN and the [HOLDE signals to time the decimal unit 730 to thepipeline operations of the control unit 704. These signals also inputthe status flag control logic 730-202 whose output inputs a decimal unitcontrol logic 730-200 as well as inputting the status flag control logic730-202 and the decimal unit control logic 730-200. Also applied to thedecimal unit control logic 730-200 are the DUCMD outputs of the decimalunit decode logic 730-204 and the descriptor information received fromcontrol unit 704-1 over signal lines RSIR 21-35 and ASFA 33-36 in theregisters shown in FIG. 3.

Operands stored in cache 750 are transferred to the operand processingunit 730-206 a word at a time over signal lines ZDI 0-35. The operandprocessing unit 730-206 is conditioned by the descriptor information,the status flag signals and the register and switch control signals,receiving the operand word from cache 750 to strip non-operand andnon-decimal digit characters from the word, converting the word into4-bit decimal digits, aligning the four 4-bit decimal digits into wordsof up to eight 4-bit decimal digits and transferring the completed wordto the execution unit 714 over signal lines RDOD 0-35. Outputting thelogic 730-200 unit are the PK-VCTR 0-3 signals and the RRLTRD, RREQRD,ADSZ and ZAMO conditional branch signals which generate branch addressesin the execution address and branch circuits 701-1.

A clock signal times the relationships between the logic units of FIG.4.

FIG. 4 shows the flow of logic through the system. Where the portions ofthe logic blocks of FIG. 4 relate to the inventions, they are shown infurther detail in FIG. 3.

FIG. 5 shows two typical instructions processed through the decimal unit730. The AD2D instruction--add using two decimal operands, adds theoperand from the address location and in the format defined bydescriptor 1 to the operand from the address location and in the formatdefined by descriptor 2 and places the resulting operand in the formatand address location defined by descriptor 2.

The AD3D instructions--add using 3 decimal operands adds the operandfrom the address location and in the format defined by descriptor 1 tothe operand from the address location and in the format defined bydescriptor 2 and places the resulting operand in the format and addresslocations defined by descriptor 3. The instruction word is made up of 36bit positions 00-35.

The instruction format includes a P bit defining EBCDIC data when aZERO, and ASC11 data when a ONE.

Fields MF1, MF2 and MF3 describe the address modifications to beperformed on descriptor 1, 2 and 3 respectively.

The T bit enables the truncation fault.

The RD bit enables the rounding operation.

The OP CODE specifies the operation to be performed. In FIG. 5 the OPCODE 202-1 specifies the AD2D instruction and OP CODE 222-1 specifiesthe AD3D instruction.

I is the interrupt inhibit bit.

For the descriptor formats, Y1, Y2 and Y3 are the main memory wordlocations of the most significant character of the operand specified bydescriptors 1, 2 and 3 respectively.

The O/E bit identifies the main memory word address as being either anodd address or an even address.

CN1, CN2 and CN3 are codes that define the position of the mostsignificant character within the main memory word of the operandspecified by descriptors 1, 2 and 3 respectively. Codes depend on thedata type as shown below:

    ______________________________________                                                   Codes    Character Numbers                                         ______________________________________                                        9 bit characters                                                                           000        0                                                                  010        1                                                                  100        2                                                                  110        3                                                     4 bit characters                                                                           000        0                                                                  001        1                                                                  010        2                                                                  011        3                                                                  100        4                                                                  101        5                                                                  110        6                                                                  111        7                                                     ______________________________________                                    

TN1, TN2 and TN3 are codes that define the numeric data type fordescriptors 1, 2 and 3 respectively. A ZERO specifies 9-bit data and aONE specifies 4-bit data.

The S1, S2 and S3 fields identify the sign and decimal type ofdescriptor 1, 2 and 3 respectively.

    ______________________________________                                        Unpacked Data     Packed Data TN = 1                                          TN = 0 OVP allowed                                                                              or OVP not allowed                                          ______________________________________                                         ##STR1##                                                                            LS, OVP, scaled                                                                               ##STR2##                                                                              Floating point, LS                             01    LS, scaled      01      LS scaled                                       10    TS, scaled      10      TS scaled                                       11    TS, OVP, scaled 11      No signs, scaled                                ______________________________________                                         LS = Leading                                                                  TS = Trailing Sign                                                            OVP = Overpunched Sign                                                   

SF1, SF2 and SF3 specify the scale factors of descriptors 1, 2 and 3respectively. The decimal point is located after the least significantdigit. A positive scale factor moves the decimal point that manypositions to the right. A negative scale factor moves the decimal pointthat many positions to the left.

N1, N2 and N3 are the number of characters in the operand defined bydescriptors 1, 2 and 3 respectively. N1, N2 and N3 may be 4-bit codeswhich specify registers that contains the length of the respectiveoperand. However, for describing the invention N1, N2 and N3 are thenumber of characters in the operand.

Decimal Unit 730--FIG. 3--Vector Branch Data

Referring to FIG. 3, the decimal unit control logic 730-20 generatescontrol signals [1PKVCTR, [2PKVCTR and [4PKVCTR in response to decimalunit 730 DUCMD command signals as described supra. The vector branchlogic 730-15 has applied to it signals indicative of the characteristicsof the operand. The output signals of decode logic 730-38 and 730-40which are described infra define the operand as a floating point oroverpunched sign and as a scaled operand if made up of 4-bit or 9-bitdecimal characters. The ZTNSA1 and ZTNSB1 signals indicate an operandwith a trailing sign if at logical ONE and an operand with a leadingsign if a logical ZERO. The ALNS 3-5 and the ALNDA 0-3 and the ALNDB 0-3signals identify the operand as having an adjusted length of greaterthan 63 decimal digits or a length of less than or equal to 63 decimaldigits. The detailed logic is shown in FIG. 8.

The vector branch logic 730-15 output signals PK-VCTR 0-3 are applied tothe execution address and branch circuits 701-1 in response to the[1PKVCTR, [2PKVCTR and [4PKVCTR control signals to indicate to theexecution control store 701-2, FIG. 1, the next microword to beprocessed by the system.

Referring to FIG. 8, a PK-VCTR switch 15-72 a-d generates vector branchsignals PK-VCTR 0-3 in response to microword signals which are appliedto the decimal unit 730. The microword signals generate DUCMD commandsignals, which when combined with status flag signals generate controlsignals [1PKVCTR, [2PKVCTR and [4PKVCTR. These control signals areapplied to the 1, 2 and 4 input select terminals of switch 15-72 andselect 1 of 8 input signals from each of 4 sections of the switch 15-72a-d.

During the processing of non-decimal numeric instructions the decimalunit 730 is inoperative thereby activating input terminal 0 of switch15-72 a-d.

The type length vector signals are applied to input terminal 1 of switch15-72 a-d. The DSHORT signal is applied to input terminal 1 of switch15-72 a. If the ALNS adder 730-24 indicates the adjusted length of theoperand as greater than or equal to binary 16 then one or more of theinput signals ALNS 3-5 to AND/NAND gates 15-32, 15-34 and 15-36respectively is at logical ONE. One or more of the output signals atlogical ZERO is applied to the inputs of a AND/NAND gate 15-38. Theoutput signal ALNSGTE 16 is applied to the input of an AND/NAND gate15-50. If this is not a decimal multiply/divide instruction then theoutput signal DLNSCLDGTE 16 is forced to logical ZERO. This signal,applied to the input of an AND/NAND gate 15-74 forces the DLONG outputsignal to logical ZERO. Signals ALNDA1, ALNDA2, ALNDB1 and ALNDB2 areapplied to the inputs of AND/NAND gates 15-40, 15-42, 15-44 and 15-46respectively. Logical ONE is applied to the other input terminals. Theoutput signals of AND/NAND gates 15-40 and 15-42 are applied to theinputs of an AND/NAND gate 15-52 and the output signals of AND/NANDgates 15-44 and 15-46 are applied to the inputs of an AND/NAND gate15-54. The output signals ALNDAGTE 16 and ALNDBGTE 16 at logical ONEindicate the length of operands 1 and 2 are less than 16 decimal digits.If the operands are not floating point operands and the adjusted lengthincluding scale factor adjustment are less than 16 decimal digits thensignal DLONG, the output of AND/NAND gate 15-74, at logical ONEindicates that both operands are processed as short operands. The DLONGsignal is applied to the input of an AND/NAND gate 15-56. The outputsignal DSHORT, at logical ONE, indicates that the operand beingprocessed is a long operand. Signal D12EQOVP is applied to the otherinput of AND/NAND gate 15-56 and when at logical ONE indicates thatneither operand 1 nor operand 2 has an overpunched sign character whichis the requirement for a short operand.

The DSHORT signal at logical ONE indicating a short operand is appliedto the input of a AND/NAND gate 15-58. Signal ZTNSAO at logical ONEindicating a 9-bit per character operand is applied to the other inputof NAND gate 15-58. The output signal DSHORT 9 at logical ZERO isapplied to an input of an AND/NAND gate 15-62. The output signalDLNGORST 9 at logical ONE is applied to the input terminal 1 of switch15-72 b indicating a short 9-bit per character operand. Logical ZERO isapplied to input terminal 1 of switches 15-72 c and d.

Signals TDB0 and TDB1 are applied to input terminals 2 and 3 of switch15-72 and 15-72 c respectively. The boolean expressions are describedsupra and indicate the number of cycles of delay between the cycle onwhich the read request is made of cache 750 and a complete word isreceived by the execution unit 714. The ARWC adder 730-60 signal ARWC 6is applied to input terminals 2 and 3 of switch 15-72 d and indicates aone word operand if at logical ZERO and a two word operand if at logicalONE.

Input terminals 4 and 6 of switch 15-72 a-d are selected for thedescriptor 1 vector and store vector operations, respectively. SignalROP-1 from control store 704-2 at logical ONE indicating an overpunchedsign operand is applied to an input of an AND/NAND gate 15-2. The ZTNSA0signal indicating a 9-bit per character operand when at logical ONE, isapplied to the other input of AND/NAND gate 15-2. Either input atlogical ZERO forces the signal D1NEW 9 which is applied to an input ofan AND/NAND gate 15-14, to logical ONE. Signals ZTNSA1 and ZTNSA2, atlogical ONE, are applied to the other inputs of AND/NAND gate 15-14.Output signal D1EQFLP at logical ZERO, indicating a floating pointoperand, is applied to the input of an AND/NAND gate 15-64. The outputsignal D1FLPORTSO at logical ONE is forced to logical ONE indicating afloating point operand.

If signals ROP-1 and ZTNSA0 are at logical ONE, the D1NEW9 signal outputof AND/NAND gate 15-2 is at logical ONE. If signal DBITX is at logicalONE then the output signal D1EQOVP of an AND/NAND gate 15-22 is atlogical ZERO. This forces the output, signal D12EQOVP, of an AND/NANDgate 15-30 to logical ONE. If signal ZTNSA1 is at logical ONE indicatinga trailing sign then the output signal D1EQTSO of a NAND gate 15-26 atlogical ZERO forces the D1FLPORTSO signal output of AND/NAND gate 15-64to logical ONE. Signal D1FLPORTSO at logical ONE is applied to inputterminals 4 and 6 of switch 15-72 b indicating a floating point oroverpunched trailing sign operand.

Signal D1EQOVP, the output of AND/NAND gate 15-22 is applied to inputterminals 4 and 6 of switch 15-72 a indicating an overpunched signoperand.

Signal DBITX is at logical ONE if signals ZTNSA1 and ZTNSA2 at logicalONE are applied to an AND/NAND gate 15-4 indicating an operand with nosign or an overpunched trailing sign or signals ZTNSA0, ZTNSA1 andZTNSA2 are applied to an AND/NAND gate 15-6 indicating a 9-bit percharacter floating point or overpunched leading sign operand. Outputsignal D1EQFLP 9 of an AND/NAND gate 15-6 at logical ZERO forces signalDBITX, the output of AND/NAND gate 15-16 to logical ONE.

Logical ZEROs are selected from terminals 4 and 6 of switches 15-72 cand d. The firmware generates a result equals zero and an overflow checkduring the store vector operation. The descriptor 2 vector selects inputterminal 5 of switch 15-72 a-d. Signal D2EQOVP is applied to terminal 5of switch 15-72 a and when at logical ONE indicates an operand with anoverpunched sign. The D2EQOVP signal is generated in a similar manner asthe D1EQOVP signal which indicates an operand 1 with an overpunchedsign.

Signal D2FLPORTSO generated in a similar manner as signal D1FLPORTSOthrough AND/NAND gates 15-28 and 15-66 and is applied to terminal 5 ofswitch 17-72 b indicating a floating point operand or an operand with anoverpunched trailing sign.

Switch 15-72 c, d input terminals 5 are at logical ZERO.

The long input vector selects input terminal 7 of switch 15-72 a-d.Signals D1EQFLP and D2EQFLP are applied to the inputs of an AND/NANDgate 15-48. The output signal D12EQFLP is applied to the inputs ofAND/NAND gates 15-60 and 15-70 and when at logical ZERO, indicating afloating point operand, forces signals D12FLPOREL and D12FLPOROVP tological ONE. The input terminal 7 of switch 15-72 a and 15-72 b atlogical ONE indicates to the firmware to execute the descriptor 1 anddescriptor 2 vectors.

If signal D12EQFLP is at logical ONE indicating scaled operands, thensignal ALNSLTE63 at logical ZERO indicating a length of less than orequal to 63 decimal digits is applied to the input of AND/NAND gates15-60 and 15-68. The output signals D12FLPOREL at logical ONE indicatesboth operands having a length of less than or equal to 63 decimaldigits. Signal D12EQOVP is applied to the other input of AND/NAND gate15-68. The output signal D12OVPL63 at logical ZERO is applied to theinput of AND/NAND gate 15-70. The output signal D12FLPOROVP at logicalONE indicates that both operands are scaled with an overpunched sign andthe lengths are less than or equal to 63 decimal characters.

Signal ALNSLTE63 at logical ZERO is generated as the output of AND/NANDgate 15-8. The input signal ALNS3 at logical ONE indicates a length ofgreater than 63 decimal digits. FMYDV is at logical ONE since this isnot a multiply/divide operation. D12EQFLP is at logical ONE sinceneither operand is a floating point operand.

While in accordance with the provisions and statute, there has beenillustrated and described the best form of the invention known, certainchanges may be made to the system described without departing from thespirit and scope of the invention as set forth in the appended claimsand that in some cases, certain features of the invention may be used toadvantage without a corresponding use of other features.

What is claimed is:
 1. A data processing system comprising:a cache memory for storing operand words and instructions, each of said operand words being coded to specify a number of types of information, said number of types of information including decimal digits, sign characters, exponent characters and non-operand information, each of said instructions including an operation code portion specifying a decimal numeric operation performed by said system and also including descriptor information for describing characteristics of said operand words; an execution control unit for storing microwords, said data processing system being responsive to said microwords for executing operations specified by said operation code portion of said instructions; a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit, said execution control unit being responsive to said operation code portion of said instruction for selecting a series of said microwords, said data processing system being responsive to said series of said microwords for executing said decimal numeric operation; a decimal unit coupled to said control unit and to said cache, said decimal unit storing said descriptor information received from said control unit and storing said operand words received from said cache, said descriptor information conditioning said decimal unit to select said decimal digits of said operand words when said operand words are transferred to said decimal unit from said cache; an execution unit coupled to said decimal unit for receiving said decimal digits in response to said series of microwords and performing said decimal numeric instruction thereby generating and transferring decimal digits specifying an arithmetic result to said decimal unit for forming resultant operand words for transfer to said cache; wherein said decimal unit includes shifter means for generating register and switch control signals for selecting said decimal digits of said operand words received from said cache, and also forming said resultant operand words received from said execution unit on the cycle said operand words are processed by said decimal unit.
 2. The system of claim 1 wherein said decimal unit comprises:decimal unit control means coupled to said control unit and responsive to control state signals for storing signals indicative of said descriptor information in said decimal unit, said decimal unit control means including said shifter means being further coupled to said execution unit and being responsive to a plurality of selected signals from said microwords and to said descriptor information signals for generating said register and switch control signals; operand processing means coupled to said cache and said execution unit and responsive to said series of said microwords for receiving said operand words from said cache, and responsive to said register and switch control signals for stripping said decimal digits from said operand words for transfer of said decimal digits of said operand words to said execution unit for processing; said operand processing means being further responsive to said series of said microwords, for receiving said decimal digits specifying an arithmetic result from said execution unit, and being responsive to said register and switch control signals for appending to said decimal digits specifying an arithmetic result, said number of types of information, thereby generating said resultant operand words for transfer to said cache.
 3. The system of claim 2 wherein said decimal unit control means comprises:decode means coupled to said execution control unit and responsive to said plurality of selected signals from said microwords, for generating a plurality of command signals; status means coupled to said decode means and responsive to said plurality of command signals, said status means being further coupled to said control unit, and responsive to a plurality of control state signals for generating a plurality of status flag signals; control means coupled to said control unit, said status means and said decode means and responsive to said plurality of control state signals, said plurality of status flag signals, said plurality of command signals and said descriptor information signals for generating said register and switch control signals, said control means being further coupled to said status means for generating said plurality of status flag signals.
 4. The system of claim 3 wherein said control means comprises:storage means coupled to said control unit and responsive to said plurality of control state signals for storing said descriptor information signals; adder means coupled to said storage means and responsive to said status flag signals and said descriptor information signals for generating pointer signals; and shifter means coupled to said adder means and responsive to said pointer signals, said descriptor information signals and said status flag signals for generating said register and switch control signals.
 5. The system of claim 4 wherein said operand processing means comprises:loading means coupled to said cache and responsive to said series of microwords for receiving said operand words from said cache; first switching means coupled to said loading means and responsive to said register and switch control signals for stripping said decimal digits from said operand words received from said cache for transfer to said execution unit for processing; said loading means being further coupled to said execution unit and responsive to said series of microwords for receiving said decimal digits specifying an arithmetic result from said execution unit; and second switching means coupled to said loading means and responsive to said register and switch control signals for appending said number of types of information to said decimal digits received from said execution unit thereby generating said resultant operand words.
 6. The system of claim 5 wherein said adder means includes left pointer load adder means coupled to said storage means and responsive to said status flag signals and first descriptor information signals for generating left pointer load adder signals indicative of the number of zeros to the left of the most significant digit of said operand word received from said cache; andwherein said adder means includes right pointer load adder means coupled to said storage means and responsive to said status flag signals and second descriptor information signals for generating right pointer load signals indicative of the number of zeros to the right of the least significant digit of said operand word received from said cache.
 7. The system of claim 6 wherein said shifter means includes left shifter load means coupled to said left pointer load adder means and responsive to said left pointer load signals for generating first ones of said register and switch control signals; andwherein said shifter means further includes right shifter load means coupled to said right pointer load adder means and responsive to said right pointer load signals for generating second ones of said register and switch control signals.
 8. The system of claim 7 wherein said first switching means coupled to said loading means for receiving a first operand word from said cache containing the most significant decimal digit includes a first stripping means responsive to said first ones of said register and switch control signals for forcing the character positions to the left of the most significant digit of said first operand word to decimal ZERO thereby stripping said sign characters and said non-operand information from said first operand word; andwherein said first switching means further includes a second stripping means coupled to said loading means for receiving a second operand word from said cache containing the least significant decimal digit and responsive to said second one of said register and switch control signals for forcing the character positions to the right of the least significant digit of said second operand word to decimal ZERO thereby stripping said sign and said exponent characters and said non-operand information from said second operand word.
 9. The system of claim 5 wherein said adder means includes sign store pointer adder means coupled to said storage means and responsive to said status flag signals and third descriptor information signals for generating sign store pointer signals indicative of the position of said sign characters in said resultant operand words; andwherein said adder means further includes exponent store pointer adder means coupled to said storage means and responsive to said status flag signals and fourth descriptor information signals for generating exponent store pointer signals indicative of the position of said exponent characters in said resultant words.
 10. The system of claim 9 wherein said shifter means includes sign store shifter means and exponent store shifter means coupled to said sign store pointer adder means and to said exponent store adder means and responsive to said sign store pointer signals and to said exponent store pointer signals for generating third and fourth ones of said register and switch control signals.
 11. The system of claim 10 wherein said adder means further includes rewrite store adder means coupled to said storage means and responsive to said status flag signals and fourth descriptor information signals for generating rewrite store pointer signals indicative of the position of said non-operand information in said resultant operand words.
 12. The system of claim 11 wherein said shifter means further includes rewrite store shifter means coupled to said rewrite store adder means and responsive to said rewrite store pointer signals for generating fourth ones of said register and switch control signals.
 13. The system of claim 12 wherein said second switching means coupled to said loading means for receiving said resultant operand words from said execution unit, includes appending means, responsive to said fourth ones of said register and switch control signals for appending said non-operand information to said resultant words.
 14. The system of claim 13 wherein said shifter means includes input means coupled to said adder means for receiving a plurality of input signals, said signals including binary ONE signals, binary ZERO signals, said descriptor information and said status flag signals; shifting means coupled to said adder means and to said input means and responsive to said descriptor information signals and to said status flags for selecting a predetermined number of adjacent signals of said plurality of input signals; andoutput means coupled to said shifting means and said input means and responsive to said predetermined number of adjacent signals for generating said register and switch control signals.
 15. A data processing system comprising:memory means for storing operand words coded to specify a number of types of information including decimal digits, sign and exponent characters and non-operand information, and instructions including descriptor information, said instructions including an operation code portion specifying a decimal numeric operation performed by said system; a decimal unit coupled to said memory means for receiving said operand words and said descriptor information in response to said decimal numeric instruction, said decimal unit including load shifter means for generating load register and switch control signals for selecting said decimal digits of said operand words; executing means coupled to said decimal unit for receiving said decimal digits of said operand words and performing said decimal numeric instruction thereby generating and transferring decimal digits specifying an arithmetic result to said decimal unit; wherein said decimal unit includes store shifter means for generating store register and switch control signals for forming resultant operand words including said decimal digits specifying said arithmetic result.
 16. The system of claim 15 wherein said decimal unit comprises:decimal unit control means coupled to said memory means and responsive to signals indicative of said operation code portion of said instructions for storing signals indicative of said descriptor information in said decimal unit, said control means including said load shifter means for generating said load register and switch control signals; operand processing means coupled to said memory means and to said executing means, and responsive to said operation code signals for receiving said operand words from said memory means, said operand processing means includes first switching means being responsive to said load register and switch control signals for selecting said decimal digits from said operand words for transfer to said executing means for processing; said control means including said store shifter means for generating said store register and control signals, said operand processing means being further responsive to said operation code signals for receiving said decimal operation code signals for receiving said decimal digits specifying said arithmetic result, said operand processing means including second switching means being responsive to said store register and control signals for appending to said decimal digits specifying said arithmetic result, said number of types of information thereby generating said resultant operand words.
 17. The system of claim 16 wherein said load shifter means includes load input means comprising a plurality of adjacent binary ONE load input signals and a plurality of binary ZERO load input signals;load shifting means coupled to said load input means and responsive to said descriptor information signals and to status flags for selecting a predetermined number of adjacent signals of said plurality of load input signals; and load output means coupled to said load shifting means and responsive to said predetermined number of adjacent signals for generating said load register and switch control signals.
 18. The system of claim 17 wherein said store shifter means includes store input means comprising a plurality of adjacent binary ONE store input signals, a plurality of adjacent binary ZERO store input signals, and signals including a plurality of descriptor information signals and status flag signals;store shifting means coupled to said store input means and responsive to said descriptor information signals and to said status flag signals for selecting a predetermined number of adjacent signals of said plurality of store input signals; and store output means coupled to said store shifting means and responsive to said predetermined number of adjacent signals for generating said store register and switch control signals. 